MC68711E20CFNE3 Freescale Semiconductor, MC68711E20CFNE3 Datasheet - Page 60

• Manufacturer Part Number: MC68711E20CFNE3
• Description: IC MCU 8BIT 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68711E20CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: M687xx
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Resets, Interrupts, and Low-Power Modes
4.4 Low-Power Operation
The M68HC11 Family of microcontroller units (MCU) has two programmable low power-consumption
modes: stop and wait. In the wait mode, the on-chip oscillator remains active. In the stop mode, the
oscillator is stopped. This subsection describes these two low power-consumption modes.
4.4.1 Stop Mode
The STOP instruction places the MCU in its lowest power-consumption mode, provided the S bit in the
CCR is cleared. In this mode, all clocks are stopped, thereby halting all internal processing.
To exit the stop mode, a low level must be applied to either the IRQ, XIRQ, or RESET pin. An external
interrupt used at IRQ is only effective if the I bit in the CCR is cleared. An external interrupt applied at the
XIRQ input is effective, regardless of the setting of the X bit of the CCR. However, the actual recovery
sequence differs, depending on the X bit setting. If the X bit is cleared, the MCU starts with the stacking
sequence leading to the normal service of the XIRQ request. If the X bit is set, the processing always
continues with the instruction immediately following the STOP instruction. A low input to the RESET pin
always results in an exit from the stop mode, and the start of MCU operations is determined by the reset
vector.
The CPU will not exit stop mode correctly when interrupted by IRQ or XIRQ if the instruction preceding
STOP is a column 4 or 5 accumulator inherent (opcodes $4X and $5X) instruction, such as NEGA, NEGB,
COMA, COMB, etc. These single-byte, two-cycle instructions must be followed by an NOP, then the
STOP command. If reset is used to exit stop mode, the CPU will respond properly.
A restart delay is required if the internal oscillator is being used. The delay allows the oscillator to stabilize
when exiting the stop mode. If a stable external oscillator is being used, the delay (DLY) bit in the OPTION
register can be cleared to bypass the delay. If the DLY bit is clear, the RESET pin would not normally be
used to exit the stop mode. The reset sequence sets the DLY bit, and the restart delay would be
reimposed.
4.4.2 Wait Mode
The wait (WAI) instruction places the MCU in a low power-consumption mode. The wait mode consumes
more power than the stop mode since the oscillator is kept running. Upon execution of the WAI instruction,
the machine state is stacked and program execution stops.
The wait state can be exited only by an unmasked interrupt or RESET. If the I bit of the CCR is set and
the COP is disabled, the timer system is turned off by WAI to further reduce power consumption. The
amount of power savings is application dependent. It also depends upon the circuitry connected to the
MCU pins, and upon subsystems such as the timer, serial peripheral interface (SPI), or serial
communications interface (SCI) that were or were not active when the wait mode was entered.
MC68HC711D3 Data Sheet, Rev. 2.1
60
Freescale Semiconductor