C8051F530-IT Silicon Laboratories Inc, C8051F530-IT Datasheet - Page 88

• Manufacturer Part Number: C8051F530-IT
• Description: IC 8051 MCU 8K FLASH 20TSSOP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F53xr

Specifications of C8051F530-IT

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.25 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 336-1343

C8051F52x/F52xA/F53x/F53xA
SFR Definition 8.4. PSW: Program Status Word
88
Bit7:
Bit6:
Bit5:
Bits4–3: RS1–RS0: Register Bank Select.
Bit2:
Bit1:
Bit0:
R/W
CY
Bit7
CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to 0 by all other arithmetic operations.
AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
These bits select which register bank is used during register accesses.
OV: Overflow Flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• A MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other
cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum
is even.
0
0
1
1
RS1
R/W
AC
Bit6
0
1
0
1
RS0
R/W
Bit5
F0
0
1
2
3
Register Bank
RS1
R/W
Bit4
0x00–0x07
0x08–0x0F
0x10–0x17
0x18–0x1F
Rev. 1.3
RS0
R/W
Bit3
Address
R/W
OV
Bit2
R/W
Bit1
F1
SFR Address: 0xD0
PARITY
Bit0
R
00000000
Addressable
Reset Value
Bit