XC705B32CFNE Freescale Semiconductor, XC705B32CFNE Datasheet - Page 206

• Manufacturer Part Number: XC705B32CFNE
• Description: IC MCU 2.1MHZ 32K OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC705B32CFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14
After reset, the MC68HC705B16 serial bootstrap routine will first echo two blocks of four bytes at
$00, as no data is programmed yet.
If the data received is $00 for EPROM locations or $FF for EEPROM locations, no programming
in the EPROM and EEPROM1 takes place, and the contents of the accessed location are returned
as a prompt. The entire EPROM/EEPROM memory can be read in this fashion (serial dump).
Warning: When using this function with a programmed device, the device must be placed into
Serial RAM loading and execute can be accomplished in this mode. A RAM byte will be written if
the address sent by the host in the serial protocol points to the RAM.
RAM bytes $008B–$00E3 and $0250–$02ED are available for user test programs. A 10-byte stack
resides at the top of RAMI, allowing, for example, one interrupt and two sub-routine levels. The
RAM addresses between $0050 and $008A are used by the loader and are therefore not available
to the user during serial loading/executing.
If the SEC bit is at ‘1’, program execution is triggered by sending a negative (bit 7 set) high
address; execution starts at address XADR ($008B).
In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see
Table
pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,
because an explicit jump (JMP) opcode is needed to cause the desired jump to the user’s service
routine address.
Freescale
E-18
E-5). This allows programmers to use their own service-routine addresses. Each
4) The exchange of data continues until the MC68HC705B16 has sent the four
5) If the data is different from $00 for EPROM or $FF for EEPROM, it is
6) Loop to 1.
data bytes and the host has sent the 2 address data bytes and 4 data bytes.
programmed at the address provided, while the next address and bytes are
received and the previous data is echoed.
RAM/EPROM/EEPROM serial bootstrap mode without EPROM erase check (PD4 = 1).
Table E-5 Bootstrap vector targets in RAM
SCI interrupt
Timer overflow
Timer output compare
Timer input capture
IRQ
SWI
Vector targets in RAM
MC68HC705B16
$02EE
$02FA
$02FD
$02F1
$02F4
$02F7
MC68HC05B6
Rev. 4.1