XC705B32CFNE Freescale Semiconductor, XC705B32CFNE Datasheet - Page 173

• Manufacturer Part Number: XC705B32CFNE
• Description: IC MCU 2.1MHZ 32K OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC705B32CFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

C.5.1
The flowchart in
to check if the EPROM is erased (all $00s). If a non $00 byte is detected, the red LED stays on
and the routine will stay in a loop. Only when the whole EPROM content is verified as erased will
the green LED be turned on.
C.5.2
When this mode is selected, the EPROM is loaded in increasing address order with non EPROM
segments being skipped by the loader. Simultaneous programming is performed by reading four
bytes of data before actual programming is performed, thus dividing the loading time of the internal
EPROM by four.
When PD2=0, the programming time is set to 5 milliseconds and the program/verify routine takes
approximately 15 seconds.
Parallel data is entered through Port A, while the 13-bit address is output on port B and PC0 to
PC4. If the data comes from an external EPROM, the handshake can be disabled by connecting
together PC5 and PC6. If the data is supplied via a parallel interface, handshaking will be provided
by PC5 and PC6 according to the timing diagram of
During programming, the green LED flashes at about 3 Hz.
Upon completion of the programming operation, the EPROM content is checked against the
external data source. If programming is verified the green LED stays on, while an error causes the
red LED to be turned on.
to load and execute data in the RAM).
Note:
MC68HC05B6
Rev. 4.1
HDSK out
HDSK in
Address
(PC5)
(PC6)
DATA
The entire EPROM can be loaded from the external source; if it is desired to leave a
segment undisturbed, the data for this segment should be all zeros.
F29
Erased EPROM verification
EPROM parallel bootstrap load
Figure C-3
Figure C-6
Figure C-5 Timing diagram with handshake
and
Figure C-4
shows a circuit that can be used to program the EPROM (or
Data read
MC68HC705B5
shows that the on-chip bootstrap routines can be used
Figure
C-5.
Data read
Freescale
C-11
14