XC705B32CFNE Freescale Semiconductor, XC705B32CFNE Datasheet - Page 176

• Manufacturer Part Number: XC705B32CFNE
• Description: IC MCU 2.1MHZ 32K OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC705B32CFNE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14
A 10-byte stack is also reserved at the top of the RAM allowing, for example, one interrupt and two
sub-routine levels.
Program execution is triggered by sending a negative (bit 7 set) high address; execution starts at
address XADR ($0083).
The RAM addresses between $0050 and $0082 are used by the loader and are therefore not
available to the user during serial loading/executing.
Refer to
C.5.4
The RAM bootstrap program will start loading the RAM with external data (e.g. from a 2564 or
2764 EPROM). Before loading a new byte, the state of the PD4/AN4 pin is checked; if this pin goes
to level ‘0’, or if the RAM is full, then control is given to the loaded program at address $0050.
If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6
according to
disabled by connecting together PC5 and PC6.
Figure C-8
programs can be loaded in turn from the EPROM. Selection is accomplished by means of the
switches connected to the EPROM higher address lines (A8 through A10). If the user program sets
PC0 to level ‘1’, the external EPROM will be disabled, rendering both port A outputs and port B
inputs available.
The EPROM parallel bootstrap loader circuit
to V
Freescale
C-14
DD
. The high order address lines will be at zero. The LEDs will stay off.
Figure C-7
shows a circuit that can be used to load the RAM with short test programs. Up to 8
Figure
RAM parallel bootstrap load and execute
shows a suitable circuit.
C-10. If the data comes from an external EPROM, the handshake can be
Table C-3 Bootstrap vector targets in RAM
SCI interrupt
Timer overflow
Timer output compare
Timer input capture
IRQ
SWI
Vector targets in RAM
MC68HC705B5
Figure C-9
(Figure
C-6) can also be used, provided VPP is tied
shows address and data bus timing.
$00EA
$00ED
$00E4
$00E7
$00F0
$00F3
MC68HC05B6
Rev. 4.1