M30280F6HP#D3 Renesas Electronics America, M30280F6HP#D3 Datasheet - Page 341

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M30280F6HP#D3

Manufacturer Part Number
M30280F6HP#D3
Description
MCU 3/5V 48K I-TEMP 80-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet

Specifications of M30280F6HP#D3

Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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M
R
R
1
e
E
Table 18.7 Errors and FMR0 Register Status
NOTE:
. v
6
J
18.8.4 Full Status Check
FMR07
0
C
(SR5)
2
9
If an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating a specific error.
Therefore, execution results can be comfirmed by verifying these status bits (full status check).
Table 18.7 lists errors and FMR0 register state. Figure 18.15 shows a flow chart of the full status check
and handling procedure for each error.
1. The flash memory enters read array mode by writing command code ‘xxFF
2 /
0 .
B
(SRD register)
FMR0 Register
1
1
0
0
8
0
of these commands. The command code written in the first bus cycle becomes invalid.
0
G
4
J
7
a
o r
status
0 -
. n
u
2
3
p
0
FMR06
, 1
0
(SR4)
(
M
2
1
0
1
0
1
0
6
7
C
2 /
page 319
, 8
Command
sequence error • A value other than ‘xxD0
Erase error
Program error
M
1
Error
6
C
2 /
f o
8
3
) B
8
5
• An incorrect commands is written
• When the block erase command is executed on an protected block
• When the program command is executed on protected blocks
• The block erase command is executed on an unprotected block
• The program command is executed on an unprotected block but
bus cycle of the block erase command
but the program operation is not successfully completed
the program operation is not successfully completed
Error occurrence condition
16
’ or ‘xxFF
16
16
(1)
’ is written in the second
’ in the second bus cycle
18. Flash Memory Version

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