MC908GR32AMFAE Freescale Semiconductor, MC908GR32AMFAE Datasheet - Page 228
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MC908GR32AMFAE
Manufacturer Part Number
MC908GR32AMFAE
Description
IC MCU 8BIT 32K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR32AMFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR32AMFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Timer Interface Module (TIM1)
17.3.1 TIM1 Counter Prescaler
The TIM1 clock source is one of the seven prescaler outputs. The prescaler generates seven clock rates
from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM1 status and control register
(T1SC) select the TIM1 clock source.
17.3.2 Input Capture
With the input capture function, the TIM1 can capture the time at which an external event occurs. When
an active edge occurs on the pin of an input capture channel, the TIM1 latches the contents of the TIM1
counter into the TIM1 channel registers, T1CHxH:T1CHxL. The polarity of the active edge is
programmable. Input captures can generate TIM1 central processor unit (CPU) interrupt requests.
228
$0023
$0024
$0025
$0026
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$002A
Addr.
TIM1 Counter Modulo Register
TIM1 Counter Modulo Register
TIM1 Channel 0 Register High
TIM1 Channel 1 Register High
TIM1 Channel 0 Register Low
TIM1 Channel 1 Register Low
TIM1 Channel 0 Status and
TIM1 Channel 1 Status and
Control Register (T1SC0)
Control Register (T1SC1)
Register Name
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
High (T1MODH)
Low (T1MODL)
See page 236.
See page 236.
See page 237.
See page 240.
See page 240.
See page 237.
See page 240.
See page 240.
(T1CH0H)
(T1CH1H)
(T1CH0L)
(T1CH1L)
Figure 17-3. TIM1 I/O Register Summary (Continued)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Bit 15
CH0F
Bit 15
CH1F
Bit 15
Bit 7
Bit 7
Bit 7
Bit 7
1
1
0
0
0
0
= Unimplemented
CH0IE
CH1IE
Bit 14
Bit 14
Bit 14
Bit 6
Bit 6
Bit 6
6
1
1
0
0
MS0B
Bit 13
Bit 13
Bit 13
Bit 5
Bit 5
Bit 5
5
1
1
0
0
0
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
MS0A
MS1A
Bit 12
Bit 12
Bit 12
Bit 4
Bit 4
Bit 4
4
1
1
0
0
ELS0B
ELS1B
Bit 11
Bit 11
Bit 11
Bit 3
Bit 3
Bit 3
3
1
1
0
0
ELS0A
ELS1A
Bit 10
Bit 10
Bit 10
Bit 2
Bit 2
Bit 2
2
1
1
0
0
Freescale Semiconductor
TOV0
TOV1
Bit 9
Bit 1
Bit 9
Bit 1
Bit 9
Bit 1
1
1
1
0
0
CH0MAX
CH1MAX
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
1
1
0
0
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