MC908GR32AMFAE Freescale Semiconductor, MC908GR32AMFAE Datasheet - Page 218

• Manufacturer Part Number: MC908GR32AMFAE
• Description: IC MCU 8BIT 32K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR32AMFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Serial Peripheral Interface (SPI) Module
CPOL — Clock Polarity Bit
CPHA — Clock Phase Bit
SPWOM — SPI Wired-OR Mode Bit
SPE — SPI Enable
SPTIE— SPI Transmit Interrupt Enable
15.12.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these conditions:
The SPI status and control register also contains bits that perform these functions:
218
This read/write bit determines the logic state of the SPSCK pin between transmissions. (See
Figure 15-5
identical CPOL values. Reset clears the CPOL bit.
This read/write bit controls the timing relationship between the serial clock and SPI data. (See
Figure 15-5
identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be high between
bytes. (See
This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins
become open-drain outputs.
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See
Resetting the
This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
•
•
•
•
•
•
•
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
1 = SPI module enabled
0 = SPI module disabled
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow error)
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
Address: $0011
Figure
and
and
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
SPI.) Reset clears the SPE bit.
Figure
Figure
15-13.) Reset sets the CPHA bit.
Figure 15-15. SPI Status and Control Register (SPSCR)
SPRF
Bit 7
0
15-7.) To transmit data between SPI modules, the SPI modules must have
15-7.) To transmit data between SPI modules, the SPI modules must have
= Unimplemented
ERRIE
6
0
OVRF
5
0
MODF
4
0
SPTE
3
1
MODFEN
2
0
SPR1
1
0
Freescale Semiconductor
SPR0
Bit 0
0
15.8