M30280F6HP#U5 Renesas Electronics America, M30280F6HP#U5 Datasheet - Page 413
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M30280F6HP#U5
Manufacturer Part Number
M30280F6HP#U5
Description
IC M16C MCU FLASH 48K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Specifications of M30280F6HP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Rev.
REVISION HISTORY
Date
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• Figure 15.13 ADCON0 to ADCON2 Registers in Repeat Mode 0 ADCON2
• Figure 15.15 ADCON0 to ADCON2 Registers in Repeat Mode 1 ADCON2
• Figure 15.17ADCON0 to ADCON2 Registers in Simultaneous Sample
• Figure 15.22 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 0
• Figure 15.23 ADTRGCON Register in Delayed Trigger Mode 0 Reserved bit
• Figure 15.27 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 1
• Figure 15.28 ADTRGON Register in Delayed Trigger Mode 1 Reserved bit
• 15.3 Sample and Hold modified
• Section deleted: [15.5 Analog Input Pin and External Sensor Equivalent Cir-
• Section deteled: [15.6 Precautions of Using A/D Converter deteled]
• 15.5 Output Impedance of Sensor under A/D Conversion added
Multi-master I
Word standardized: ACK-CLK bit
Symbol used for registers
• Table 16.1 Multi-master I
• Figure 16.3 S00 and S20 Register S00 register: Note 1 modified
• Figure 16.4 S1D0 Register Reserved bit map modified
• Figure 16.5 S10 Register b7-b6 modified
• Figure 16.6 S3D0 Register Note 1 and note 2 added, b7-b6 function modified
• Figure 16.7 S4D0 Register Note 1 added, reserved bit map modified
• 16.1 I
• Table 16.3 Set Values of S20 Register and SCL freqency Title modified
• 16.5.1 Bit 0: Last Receive Bit (LRB) modified
• 16.5.2 Bit 1: General call detection flag (ADR0) modified, note 1 modified
• 16.5.3 Bit 2: Slave address comparison flag (AAS) modified
• 16.5.5 Bit 4: I
• 16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select
register: b2-b1 function modified
register: b2-b1 function modified
Sweep Mode ADCON1 register: reserved bit map modified; ADCON2 register:
b2-b1 function modified
Reserved bit map modified; ADCON1 register: b7-b6 modified; ADCON2 regis-
ter: b2-b1 function modified
map modified
Reserved bit map modified; ADCON1 register: b7-b6 modified; b2-b1 function
modified
map modified
cuit Example]
Bit: TRX) modified
2
C Data Shift Register (S00 Register) modified
M16C/28 Group (M16C/28, M16C/28B) Hardware Manual
2
2
C bus Interface
C Bus Interface Interrupt Request Bit (PIN) modified
C-6
Description
2
C bus Interface Functions I/O pin added
Summary
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