M30280F6HP#U5 Renesas Electronics America, M30280F6HP#U5 Datasheet - Page 293
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M30280F6HP#U5
Manufacturer Part Number
M30280F6HP#U5
Description
IC M16C MCU FLASH 48K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Specifications of M30280F6HP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Table 16.7 Examples of Time-out Detection Period
0
16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE)
16.7.2 Bit1: Time-Out Detection Flag (TOF )
16.7.3 Bit2: Time-Out Detection Period Select Bit (TOSEL)
16.7.4 Bits 3,4,5: I
16.7.5 Bit7: STOP Condition Detection Interrupt Request Bit (SCPIN)
C
2
9
The TOE bit enables the time-out detection function. When the TOE bit is set to "1", time-out is detected
and the I
The internal counter measures the time-out detection time and the TOSEL bit selects between two
modes, long time and short time. When time-out is detected, set the ES0 bit to "0" (I
disabled) and reset the counter.
The TOF flag indicates the time-out detection. If the internal counter which measures the time-out
period overflows, the TOF flag is set to “1” and the I
same time.
The TOSEL bit selects time-out detection period from long time mode and short time mode. When the
TOSEL bit is set to "0", long time mode is selected. When it is set to "1", short time mode is selected,
respectively. The internal counter increments as a 16-bit counter in long time mode, while the counter
increments as a 14-bit counter in short time mode, based on the I
source. Table 16.7 shows examples of time-out detection period.
The ICK4 to 2 bits, ICK1 and ICK0 bits in the S3D0 register, and the PCLK0 bit in the PCLKR register
select the system clock (V
The SCPIN bit monitors the stop condition detection interrupt. The SCPIN bit is set to “1” when the I
bus interface interrupt is generated by detecting the STOP condition. When this bit is set to "0" by pro-
gram, it becomes "0". However, no change occurs even if it is set to "1".
0 .
2 /
B
0
0
8
0
1) the BB flag in the S10 register is set to "1" (bus busy)
2) the SCL clock stops for time-out detection period while high-level ("H") signal is maintained (see
4
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J
7
a
V
o r
0 -
. n
Table 16.7)
IIC
u
2
3
2
4
2
1
p
0
(MHz)
, 1
C bus interface interrupt request is generated when the following conditions are met.
0
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M
2
0
1
0
6
7
C
2 /
page 271
, 8
2
M
C System Clock Select Bits (ICK2-4)
1
6
IIC
C
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2 /
) of the I
8
3
) B
8
Long time mode
5
16.4
32.8
65.6
2
C bus interface circuit. See Table 16.6 for the setting values.
2
C bus interface interrupt request is generated at the
(Unit: ms)
Short time mode
16.4
16. MULTI-MASTER I
4.1
8.2
2
C system clock (V
2
2
IIC
C bus INTERFACE
C bus interface
) as a counter
2
C
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