M30280F6HP#U5 Renesas Electronics America, M30280F6HP#U5 Datasheet - Page 283
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M30280F6HP#U5
Manufacturer Part Number
M30280F6HP#U5
Description
IC M16C MCU FLASH 48K 80LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Specifications of M30280F6HP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
71
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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e
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1
NOTES:
. v
J
6
Table 16.3 Setting values of S20 register and SCL frequency
Setting value of CCR4 to CCR0
0
CCR4 CCR3 CCR2 CCR1 CCR0
C
2
9
0
0
0
0
0
0
0
1
1
1
0 .
2 /
B
0
0
1. The duty of the SCL clock output is 50 %. The duty becomes 35 to 45 % only when high-speed
2. Each value of the SCL frequency exceeds the limit at V
3. The data formula of SCL frequency is described below:
8
0
4
G
J
clock mode is selected and the CCR value = 5 (400 kHz, at VIIC = 4 MHz). “H” duration of the
clock fluctuates from –4 to +2 I
–2 to +2 I
frequency does not increase because the “L” is extended instead of “H” reduction. These are the
values when the SCL clock synchronization by the synchronous function is not performed. The
CCR value is the decimal notation value of the CCR4 to CCR0 bits.
setting values, use V
Do not set 0 to 2 as the CCR value regardless of the VIIC frequency. Set 100 kHz (max.) in
standard clock mode and 400 kHz (max.) in high-speed clock mode to the SCL frequency by
setting the CCR4 to CCR0 bits.
7
a
o r
0 -
V
V
V
. n
0
0
0
0
0
0
0
1
1
1
u
IIC
IIC
IIC
2
3
p
0
, 1
/(8 x CCR value) Standard clock mode
/(4 x CCR value) High-speed clock mode (CCR value
/(2 x CCR value) High-speed clock mode (CCR value = 5)
0
(
M
2
0
1
2
0
6
0
0
0
0
1
1
1
1
1
1
C system clock cycles in high-speed clock mode. In the case of negative fluctuation, the
7
C
2 /
page 261
, 8
0
0
1
1
0
0
1
0
1
1
M
1
6
IIC
C
f o
2 /
= 4 MHz or less. Refer to Figure 16.6.
0
1
0
1
0
1
0
1
0
1
8
3
) B
8
5
2
C system clock cycles in standard clock mode, and fluctuates from
Standard clock mode
Setting disabled
Setting disabled
Setting disabled
500 / CCR value
SCL frequency (at V
100
83.3
17.2
16.6
16.1
-
-
(2)
(2)
(3)
IIC
IIC
=4MHz, unit : kHz)
= 4 MHz or more. When using these
16. MULTI-MASTER I
5)
High-speed clock mode
Setting disabled
Setting disabled
Setting disabled
333
250
1000 / CCR value
400
166
34.5
33.3
32.3
(3)
(1)
2
C bus INTERFACE
(3)
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