HD64F3694FY Renesas Electronics America, HD64F3694FY Datasheet - Page 288
HD64F3694FY
Manufacturer Part Number
HD64F3694FY
Description
IC H8 MCU FLASH 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3694GFYV.pdf
(452 pages)
Specifications of HD64F3694FY
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3694FYJV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F3694FYV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 15 I
15.4.8
Flowcharts in respective modes that use the I
Rev.5.00 Nov. 02, 2005 Page 258 of 418
REJ09B0028-0500
Example of Use
2
C Bus Interface 2 (IIC2)
No
No
No
Write transmit data in ICDRT
Write transmit data in ICDRT
No
No
No
Set MST to 1 and TRS
Read ACKBR in ICIER
Read BBSY in ICCR2
Read TEND in ICSR
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Clear STOP in ISCR
Read STOP in ICSR
Clear TDRE in ICSR
Figure 15.17 Sample Flowchart for Master Transmit Mode
Write transmit data
Set MST and TRS
Write 1 to BBSY
Write 0 to BBSY
to 0 in ICCR1
in ICCR1 to 1.
and 0 to SCP.
ACKBR=0 ?
BBSY=0 ?
TEND=1 ?
TDRE=1 ?
Last byte?
TEND=1 ?
STOP=1 ?
in ICDRT
Transmit
Initialize
and SCP
mode?
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Mater receive mode
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Wait for last byte to be transmitted.
[11] Clear the TEND flag.
[12] Clear STOP flag.
[13] Issue the stop condition.
[14] Wait for the creation of stop condition.
[15] Set slave receive mode. Clear TDRE.
Test the status of the SCL and SDA lines.
Set master transmit mode.
Issue the start condition.
Set the first byte (slave address + R/W) of transmit data.
Wait for 1 byte to be transmitted.
Test the acknowledge transferred from the specified slave device.
Set the second and subsequent bytes (except for the final byte) of transmit data.
Wait for ICDRT empty.
Set the last byte of transmit data.
2
C bus interface are shown in figures 15.17 to 15.20.
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