HD64F2319VTE25 Renesas Electronics America, HD64F2319VTE25 Datasheet - Page 842
HD64F2319VTE25
Manufacturer Part Number
HD64F2319VTE25
Description
IC H8S MCU FLASH 512K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2319VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2319VTE25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 19 Power-Down Modes
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made
to software standby mode. When software standby mode is cleared by an external interrupt,
medium-speed mode is restored.
When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is
cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 19.1 shows the timing for transition to and clearance of medium-speed mode.
19.4
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters
sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers
are retained. Other supporting modules do not stop.
Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program
execution state via the exception handling state. Sleep mode is not cleared if interrupts are
disabled, or if interrupts other than NMI are masked by the CPU.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Rev.7.00 Feb. 14, 2007 page 808 of 1108
REJ09B0089-0700
φ,
supporting module
clock
Bus master clock
Internal address bus
Internal write signal
Sleep Mode
Figure 19.1 Medium-Speed Mode Transition and Clearance Timing
SCKCR
Medium-speed mode
SCKCR
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