C8051F130 Silicon Laboratories Inc, C8051F130 Datasheet - Page 336
C8051F130
Manufacturer Part Number
C8051F130
Description
IC 8051 MCU 128K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F130
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1147
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336
Bit7:
Bits6–4: UNUSED. Read = 000b, Write = don't care.
Bits3–1: CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
Bit0:
CIDL
R/W
Bit7
CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
These bits select the timebase source for the PCA0 counter
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
CPS2
0
0
0
0
1
1
1
1
R/W
Bit6
-
CPS1
0
0
1
1
0
0
1
1
SFR Definition 24.2. PCA0MD: PCA0 Mode
R/W
Bit5
-
CPS0
0
1
0
1
0
1
0
1
R/W
Bit4
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock
divided by 4)
System clock
External clock divided by 8 (synchronized with system clock)
Reserved
Reserved
-
Rev. 1.4
CPS2
R/W
Bit3
CPS1
R/W
Bit2
Timebase
CPS0
R/W
Bit1
SFR Address:
SFR Page:
ECF
R/W
Bit0
0xD9
0
00000000
Reset Value
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