C8051F130 Silicon Laboratories Inc, C8051F130 Datasheet - Page 304
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C8051F130
Manufacturer Part Number
C8051F130
Description
IC 8051 MCU 128K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F130
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1147
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304
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
S1MODE
R/W
Bit7
S1MODE: Serial Port 1 Operation Mode.
This bit selects the UART1 Operation Mode.
0: Mode 0: 8-bit UART with Variable Baud Rate
1: Mode 1: 9-bit UART with Variable Baud Rate
UNUSED. Read = 1b. Write = don’t care.
MCE1: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode.
Mode 0: Checks for valid stop bit.
Mode 1: Multiprocessor Communications Enable.
REN1: Receive Enable.
This bit enables/disables the UART receiver.
0: UART1 reception disabled.
1: UART1 reception enabled.
TB81: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It
is not used in 8-bit UART Mode. Set or cleared by software as required.
RB81: Ninth Receive Bit.
RB81 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th
data bit in Mode 1.
TI1: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART1 (after the 8th bit in 8-
bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART1
interrupt is enabled, setting this bit causes the CPU to vector to the UART1 interrupt service
routine. This bit must be cleared manually by software
RI1: Receive Interrupt Flag.
Set to ‘1’ by hardware when a byte of data has been received by UART1 (set at the STOP bit
sampling time). When the UART1 interrupt is enabled, setting this bit to ‘1’ causes the CPU
to vector to the UART1 interrupt service routine. This bit must be cleared manually by soft-
ware.
R/W
Bit6
-
0: Logic level of stop bit is ignored.
1: RI1 will only be activated if stop bit is logic level 1.
0: Logic level of ninth bit is ignored.
1: RI1 is set and an interrupt is generated only when the ninth bit is logic 1.
SFR Definition 22.1. SCON1: Serial Port 1 Control
MCE1
R/W
Bit5
REN1
R/W
Bit4
Rev. 1.4
TB81
R/W
Bit3
RB81
R/W
Bit2
R/W
TI1
Bit1
SFR Address:
SFR Page:
R/W
RI1
Bit0
0x98
1
01000000
Addressable
Reset Value
Bit
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