C8051F130 Silicon Laboratories Inc, C8051F130 Datasheet
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C8051F130
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C8051F130 Summary of contents
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... High Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instruction set system clocks - 100 MIPS or 50 MIPS throughput with on-chip PLL - 2-cycle MAC engine (C8051F120/1/2/3 and C8051F130/1/2/3 only) Memory - 8448 bytes internal data RAM ( 256) - 128 Banked Flash; in-system programma- ble in 1024-byte sectors - ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2 OTES 2 Rev. 1.4 ...
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... Analog Multiplexer and PGA............................................................................. 91 7.2. ADC2 Modes of Operation................................................................................ 92 7.2.1. Starting a Conversion............................................................................... 92 7.2.2. Tracking Modes........................................................................................ 92 7.2.3. Settling Time Requirements ..................................................................... 94 7.3. ADC2 Programmable Window Detector ......................................................... 100 7.3.1. Window Detector In Single-Ended Mode ............................................... 100 7.3.2. Window Detector In Differential Mode.................................................... 101 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 3 ...
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... Update Output Based on Timer Overflow .............................................. 106 8.2. DAC Output Scaling/Justification .................................................................... 106 9. Voltage Reference ................................................................................................ 113 9.1. Reference Configuration on the C8051F120/2/4/6 ......................................... 113 9.2. Reference Configuration on the C8051F121/3/5/7 ......................................... 115 9.3. Reference Configuration on the C8051F130/1/2/3 ......................................... 117 10. Comparators ......................................................................................................... 119 11. CIP-51 Microcontroller ......................................................................................... 127 11.1.Instruction Set................................................................................................. 129 11.1.1.Instruction and CPU Timing ................................................................... 129 11 ...
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... MOVX Example ............................................................................. 219 17.2.Configuring the External Memory Interface .................................................... 219 17.3.Port Selection and Configuration.................................................................... 220 17.4.Multiplexed and Non-multiplexed Selection.................................................... 222 17.4.1.Multiplexed Configuration....................................................................... 222 17.4.2.Non-multiplexed Configuration............................................................... 223 17.5.Memory Mode Selection................................................................................. 224 17.5.1.Internal XRAM Only ............................................................................... 224 17.5.2.Split Mode without Bank Select.............................................................. 224 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 5 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 17.5.3.Split Mode with Bank Select................................................................... 225 17.5.4.External Only.......................................................................................... 225 17.6.EMIF Timing ................................................................................................... 225 17.6.1.Non-multiplexed Mode ........................................................................... 227 17.6.2.Multiplexed Mode ................................................................................... 230 18. Port Input/Output.................................................................................................. 235 18.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 238 18.1.1.Crossbar Pin Assignment and Allocation ............................................... 238 18.1.2.Configuring the Output Modes of the Port Pins...................................... 239 18 ...
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... Modules ............................................................................ 328 24.2.1.Edge-triggered Capture Mode................................................................ 329 24.2.2.Software Timer (Compare) Mode........................................................... 330 24.2.3.High Speed Output Mode....................................................................... 331 24.2.4.Frequency Output Mode ........................................................................ 332 24.2.5.8-Bit Pulse Width Modulator Mode......................................................... 333 24.2.6.16-Bit Pulse Width Modulator Mode....................................................... 334 24.3.Register Descriptions for PCA0...................................................................... 335 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 7 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 25. JTAG (IEEE 1149.1) .............................................................................................. 341 25.1.Boundary Scan ............................................................................................... 342 25.1.1.EXTEST Instruction................................................................................ 343 25.1.2.SAMPLE Instruction ............................................................................... 343 25.1.3.BYPASS Instruction ............................................................................... 343 25.1.4.IDCODE Instruction................................................................................ 343 25.2.Flash Programming Commands..................................................................... 344 25.3.Debug Support ............................................................................................... 347 Document Change List............................................................................................. 349 Contact Information.................................................................................................. 350 8 Rev. 1.4 ...
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... Absolute Maximum Ratings 3. Global DC Electrical Characteristics 4. Pinout and Package Definitions Figure 4.1. C8051F120/2/4/6 Pinout Diagram (TQFP-100) ..................................... 49 Figure 4.2. C8051F130/2 Pinout Diagram (TQFP-100) ........................................... 50 Figure 4.3. TQFP-100 Package Drawing ................................................................. 51 Figure 4.4. C8051F121/3/5/7 Pinout Diagram (TQFP-64) ....................................... 52 Figure 4.5. C8051F131/3 Pinout Diagram (TQFP-64) ............................................. 53 Figure 4.6. TQFP-64 Package Drawing ................................................................... 54 5 ...
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... Voltage Reference Figure 9.1. Voltage Reference Functional Block Diagram (C8051F120/2/4/6) ...... 114 Figure 9.2. Voltage Reference Functional Block Diagram (C8051F121/3/5/7) ...... 115 Figure 9.3. Voltage Reference Functional Block Diagram (C8051F130/1/2/3) ...... 117 10. Comparators Figure 10.1. Comparator Functional Block Diagram .............................................. 119 Figure 10.2. Comparator Hysteresis Plot ............................................................... 121 11 ...
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... Figure 19.6. Typical Slave Transmitter Sequence.................................................. 263 Figure 19.7. Typical Slave Receiver Sequence...................................................... 263 20. Enhanced Serial Peripheral Interface (SPI0) Figure 20.1. SPI Block Diagram ............................................................................. 273 Figure 20.2. Multiple-Master Mode Connection Diagram ....................................... 276 Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 276 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 11 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Figure 20.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 276 Figure 20.5. Master Mode Data/Clock Timing ........................................................ 278 Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 279 Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 279 Figure 20.8. SPI Master Timing (CKPHA = 0)........................................................ 283 Figure 20 ...
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... Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings .................................................................... 38 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics (C8051F120/1/2/3 and C8051F130/1/2/3) ............................................. 39 Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7) ....................... 40 4. Pinout and Package Definitions Table 4.1. Pin Definitions ......................................................................................... 41 5. ADC0 (12-Bit ADC, C8051F120/1/4/5 Only) Table 5 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 18. Port Input/Output Table 18.1. Port I/O DC Electrical Characteristics ................................................. 236 19. System Management Bus / I2C Bus (SMBus0) Table 19.1. SMB0STA Status Codes and States .................................................. 270 20. Enhanced Serial Peripheral Interface (SPI0) Table 20.1. SPI Slave Timing Parameters ............................................................ 285 21. UART0 Table 21.1. UART0 Modes .................................................................................... 288 Table 21 ...
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... SFR Definition 8.6. DAC1CN: DAC1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 SFR Definition 9.1. REF0CN: Reference Control (C8051F120/2/4/ 114 SFR Definition 9.2. REF0CN: Reference Control (C8051F121/3/5/ 116 SFR Definition 9.3. REF0CN: Reference Control (C8051F130/1/2/ 117 SFR Definition 10.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . 122 SFR Definition 10.2. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . 123 SFR Definition 10 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 11.4. SFRNEXT: SFR Next Register . . . . . . . . . . . . . . . . . . . . . . . . . 143 SFR Definition 11.5. SFRLAST: SFR Last Register . . . . . . . . . . . . . . . . . . . . . . . . . 143 SFR Definition 11.6. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SFR Definition 11.7. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SFR Definition 11.8. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SFR Definition 11 ...
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... SFR Definition 23.1. TCON: Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 SFR Definition 23.2. TMOD: Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 SFR Definition 23.3. CKCON: Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 SFR Definition 23.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 SFR Definition 23.5. TL1: Timer 1 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2 217 Rev. 1.4 17 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 23.6. TH0: Timer 0 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 SFR Definition 23.7. TH1: Timer 1 High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 SFR Definition 23.8. TMRnCN: Timer 2, 3, and 4 Control . . . . . . . . . . . . . . . . . . . . . 321 SFR Definition 23.9. TMRnCF: Timer 2, 3, and 4 Configuration . . . . . . . . . . . . . . . . 322 SFR Definition 23.10. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte . . . . . 323 SFR Definition 23 ...
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... True 8-bit 500 ksps ADC with PGA and 8-channel analog multiplexer (C8051F12x Family) • Two 12-bit DACs with programmable update scheduling (C8051F12x Family) • 2-cycle Multiply and Accumulate Engine (C8051F120/1/2/3 and C8051F130/1/2/3) • 128 in-system programmable Flash memory • 8448 ( 256) bytes of on-chip RAM • ...
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... C8051F127-GQ 50 128 k 8448 - C8051F130 100 128 k 8448 C8051F130-GQ 100 128 k 8448 C8051F131 100 128 k 8448 C8051F131-GQ 100 128 k 8448 C8051F132 100 64 k 8448 ...
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... Prog 100 ksps AIN0.4 Gain U AIN0.5 (12-Bit) X AIN0.6 AIN0.7 TEMP SENSOR CP0+ CP0 CP0- CP1+ CP1 CP1- Figure 1.1. C8051F120/124 Block Diagram C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Port I/O Config. UART0 SFR Bus UART1 SMBus 8 SPI Bus 256 byte PCA 0 RAM Timers XRAM Timer 3/ 1 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 VDD VDD VDD Digital Power DGND DGND DGND AV+ Analog Power AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO Reset RST VDD WDT MONEN Monitor External Oscillator XTAL1 Circuit XTAL2 PLL System Clock Circuitry Calibrated Internal Oscillator VREF ...
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... AIN0.4 Gain U AIN0.5 (10-Bit) X AIN0.6 AIN0.7 TEMP SENSOR CP0+ CP0 CP0- CP1+ CP1 CP1- Figure 1.3. C8051F122/126 Block Diagram C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Port I/O Config. UART0 SFR Bus UART1 SMBus 8 SPI Bus 256 byte PCA 0 RAM Timers XRAM Timer 3/ RTC ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 VDD VDD VDD Digital Power DGND DGND DGND AV+ Analog Power AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO Reset RST VDD WDT MONEN Monitor External Oscillator XTAL1 XTAL2 Circuit PLL System Circuitry Clock Calibrated Internal Oscillator VREF ...
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... AIN0.3 M Prog 100ksps AIN0.4 Gain U AIN0.5 (10-Bit) X AIN0.6 AIN0.7 TEMP SENSOR CP0+ CP0 CP0- CP1+ CP1 CP1- Figure 1.5. C8051F130/132 Block Diagram C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Port I/O Config. UART0 SFR Bus UART1 SMBus 8 SPI Bus 256 byte PCA 0 RAM Timers 8kbyte XRAM ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 VDD VDD VDD Digital Power DGND DGND DGND AV+ Analog Power AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO Reset RST VDD WDT MONEN Monitor External Oscillator XTAL1 Circuit XTAL2 PLL System Circuitry Clock Calibrated Internal Oscillator VREF ...
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... The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 Number of Instructions 26 With the CIP-51's maximum system clock at 100 MHz, the C8051F120/1/2/3 and C8051F130/1/2/3 have a peak throughput of 100 MIPS (the C8051F124/5/6/7 have a peak throughput of 50 MIPS). C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 2 2/3 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 1.1.3. Additional Features Several key enhancements are implemented in the CIP-51 core and peripherals to improve overall perfor- mance and ease of use in end applications. The extended interrupt handler provides 20 interrupt sources into the CIP-51 (as opposed to 7 for the stan- dard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput ...
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... EMIF). The EMIF is also configurable for multiplexed or non-multiplexed address/data lines. On the C8051F12x and C8051F130/1, the MCU’s program memory consists of 128 k bytes of banked Flash memory. The 1024 bytes from addresses 0x1FC00 to 0x1FFFF are reserved. On the C8051F132/3, the MCU’s program memory consists bytes of Flash memory. This memory may be reprogrammed in-system in 1024 byte sectors, and requires no special off-chip programming voltage ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 1.3. JTAG Debug and Boundary Scan JTAG boundary scan and debug circuitry is included which provides non-intrusive, full speed, in-circuit debugging using the production part installed in the end application, via the four-pin JTAG interface. The JTAG port is fully compliant to IEEE 1149.1, providing full boundary scan for test and manufacturing pur- poses ...
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... MAC (Multiply and Accumulate) Engine The C8051F120/1/2/3 and C8051F130/1/2/3 devices include a multiply and accumulate engine which can be used to speed up many mathematical operations. MAC0 contains a 16-by-16 bit multiplier and a 40-bit adder, which can perform integer or fractional multiply-accumulate and multiply operations on signed input values in two SYSCLK cycles ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 1.5. Programmable Digital I/O and Crossbar The standard 8051 8-bit Ports ( and 3) are available on the MCUs. The devices in the larger (100- pin TQFP) packaging have 4 additional ports ( and 7) for a total of 64 general-purpose port I/O. The Port I/O behave like the standard 8051 with a few enhancements. ...
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... I2C. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little intervention by the CPU. The serial buses do not "share" resources such as timers, interrupts, or Port I/O, so any or all of the serial buses may be used together with any other. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 16-Bit Counter/Timer Capture/Compare Capture/Compare ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 1. 10-Bit Analog to Digital Converter All devices include either 10-bit SAR ADC (ADC0) with a 9-channel input multiplexer and program- mable gain amplifier. With a maximum throughput of 100 ksps, the 12 and 10-bit ADCs offer true 12-bit lin- earity with an INL of ±1LSB. The ADC0 voltage reference can be selected from an external VREF pin, or (on the C8051F12x devices) the DAC0 output. On the 100-pin TQFP devices, ADC0 has its own dedicated Voltage Reference input pin ...
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... SFR upon completion. Analog Multiplexer AIN2.0 AIN2.1 Programmable Gain AIN2.2 AIN2.3 8-to-1 AIN2.4 AMUX AIN2.5 AIN2.6 AIN2.7 Figure 1.14. 8-Bit ADC Diagram C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Configuration, Control, and Data Registers Amplifier 8-Bit AV+ + SAR X - ADC External VREF Pin VREF Start Conversion AV+ Rev ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 1.10. 12-bit Digital to Analog Converters The C8051F12x devices have two integrated 12-bit Digital to Analog Converters (DACs). The MCU data and control interface to each DAC is via the Special Function Registers. The MCU can place either or both of the DACs in a low power shutdown mode. ...
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... The output state of the comparators can be polled in software or routed to Port I/O pins via the Crossbar. The comparators can be programmed to a low power shutdown mode when not in use. CPn Output (Port I/O) 2 Comparators CPn+ CPn- Figure 1.16. Comparator Block Diagram C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 CROSSBAR SFR's + CPn (Data - and Control) Rev. 1.4 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Pin (except V and Port I/O) with DD Respect to DGND Voltage on any Port I/O Pin or RST with Respect to DGND Voltage on V with Respect to DGND ...
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... Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics (C8051F120/1/2/3 and C8051F130/1/2/3) –40 to +85 °C, 100 MHz System Clock unless otherwise specified. Parameter 1 SYSCLK = MHz Analog Supply Voltage SYSCLK > 50 MHz Analog Supply Current Internal REF, ADCs, DACs, Com- parators all active ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7) –40 to +85 °C, 50 MHz System Clock unless otherwise specified. Parameter 1 Analog Supply Voltage Analog Supply Current Internal REF, ADC, DAC, Com- parators all active Analog Supply Current with Internal REF, ADC, DAC, Com- ...
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... TDO 4 61 RST 5 62 XTAL1 26 17 XTAL2 27 18 MONEN 28 19 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 4.1. Pin Definitions ‘F131 Type ‘F133 37, 24, Digital Supply Voltage. Must be tied to +2.7 to 41, 57 +3.6 V. 38, 25, Digital Ground. Must be tied to Ground. 40 Analog Supply Voltage. Must be tied to +2.7 to +3.6 V. ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 4.1. Pin Definitions (Continued) Pin Numbers ‘F120 ‘F121 ‘F130 Name ‘F122 ‘F123 ‘F132 ‘F124 ‘F125 ‘F126 ‘F127 VREF 12 7 VREFA 8 VREF0 16 VREF2 17 VREFD 15 AIN0 AIN0 AIN0 AIN0 AIN0 AIN0 AIN0 AIN0 CP0 CP0 CP1 CP1– DAC0 100 ...
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... AIN2.0/A8/P1 AIN2.1/A9/P1 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 ‘F131 Type Description ‘F133 A Out Digital to Analog Converter 1 Voltage Output. (See DAC Specification for complete descrip- tion I/O Port 0.0. See Port Input/Output section for com- plete description I/O Port 0.1. See Port Input/Output section for com- plete description ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 4.1. Pin Definitions (Continued) Pin Numbers ‘F120 ‘F121 ‘F130 Name ‘F122 ‘F123 ‘F132 ‘F124 ‘F125 ‘F126 ‘F127 AIN2.2/A10/P1 AIN2.3/A11/P1 AIN2.4/A12/P1 AIN2.5/A13/P1 AIN2.6/A14/P1 AIN2.7/A15/P1 A8m/A0/P2 A9m/A1/P2 A10m/A2/P2 A11m/A3/P2 A12m/A4/P2 A13m/A5/P2 A14m/A6/P2 A15m/A7/P2 ‘F131 Type ‘F133 Port 1.2. See Port Input/Output section for com- D I/O plete description ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 ‘F131 Type Description ‘F133 47 D I/O Bit 0 External Memory Address/Data bus (Multi- plexed mode) Bit 0 External Memory Data bus (Non-multi- plexed mode) Port 3.0 See Port Input/Output section for complete description I/O Port 3.1. See Port Input/Output section for com- plete description ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 4.1. Pin Definitions (Continued) Pin Numbers ‘F120 ‘F121 ‘F130 Name ‘F122 ‘F123 ‘F132 ‘F124 ‘F125 ‘F126 ‘F127 ALE/P4.5 93 RD/P4.6 92 WR/P4.7 91 A8/P5.0 88 A9/P5.1 87 A10/P5.2 86 A11/P5.3 85 A12/P5.4 84 A13/P5.5 83 A14/P5.6 82 A15/P5 ‘F131 Type ‘F133 93 D I/O ALE Strobe for External Memory Address bus (multiplexed mode) Port 4 ...
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... AD2/D2/P7 AD3/D3/P7 AD4/D4/P7 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 ‘F131 Type Description ‘F133 D I/O Bit 8 External Memory Address bus (Multiplexed mode) Bit 0 External Memory Address bus (Non-multi- plexed mode) Port 6.0 See Port Input/Output section for complete description. D I/O Port 6.1. See Port Input/Output section for com- plete description ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 4.1. Pin Definitions (Continued) Pin Numbers ‘F120 ‘F121 ‘F130 Name ‘F122 ‘F123 ‘F132 ‘F124 ‘F125 ‘F126 ‘F127 AD5/D5/P7.5 67 AD6/D6/P7.6 66 AD7/D7/P7 100 48 ‘F131 Type ‘F133 67 D I/O Port 7.5. See Port Input/Output section for com- plete description I/O Port 7.6. See Port Input/Output section for com- plete description ...
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... VREF 12 AGND 13 AV+ 14 VREFD 15 VREF0 16 VREF2 17 AIN0.0 18 AIN0.1 19 AIN0.2 20 AIN0.3 21 AIN0.4 22 AIN0.5 23 AIN0.6 24 AIN0.7 25 Figure 4.1. C8051F120/2/4/6 Pinout Diagram (TQFP-100) C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 C8051F120 C8051F122 C8051F124 C8051F126 Rev. 1.4 75 A13m/A5/P6.5 74 A14m/A6/P6.6 73 A15m/A7/P6.7 72 AD0/D0/P7.0 71 AD1/D1/P7.1 70 AD2/D2/P7.2 69 AD3/D3/P7.3 68 AD4/D4/P7.4 67 AD5/D5/P7.5 66 AD6/D6/P7.6 65 AD7/D7/P7.7 64 VDD 63 DGND 62 P0 ...
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... CP0- 8 CP0+ 9 AGND 10 AV+ 11 VREF 12 AGND 13 AV VREF0 AIN0.0 18 AIN0.1 19 AIN0.2 20 AIN0.3 21 AIN0.4 22 AIN0.5 23 AIN0.6 24 AIN0.7 25 Figure 4.2. C8051F130/2 Pinout Diagram (TQFP-100) 50 C8051F130 C8051F132 Rev. 1.4 75 A13m/A5/P6.5 74 A14m/A6/P6.6 73 A15m/A7/P6.7 72 AD0/D0/P7.0 71 AD1/D1/P7.1 70 AD2/D2/P7.2 69 AD3/D3/P7.3 68 AD4/D4/P7.4 67 AD5/D5/P7.5 66 AD6/D6/P7.6 65 AD7/D7/P7.7 64 VDD 63 DGND 62 P0 ...
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... PIN 1 DESIGNATOR Figure 4.3. TQFP-100 Package Drawing C8051F120/1/2/3/4/5/6/7 C8051F130/1/2 Rev. 1.4 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0. 16. 14. 0. 16. 14. 0.45 0.60 0.75 51 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 CP1- 1 CP1+ 2 CP0- 3 CP0+ 4 AGND 5 AV+ 6 VREF 7 VREFA 8 AIN0.0 9 AIN0.1 10 AIN0.2 11 AIN0.3 12 AIN0.4 13 AIN0.5 14 AIN0.6 15 AIN0.7 16 Figure 4.4. C8051F121/3/5/7 Pinout Diagram (TQFP-64) 52 C8051F121 C8051F123 C8051F125 C8051F127 Rev. 1.4 48 /WR/P0.7 47 AD0/D0/P3.0 46 AD1/D1/P3.1 45 AD2/D2/P3.2 44 AD3/D3/P3.3 43 AD4/D4/P3.4 42 AD5/D5/P3.5 41 VDD 40 DGND 39 AD6/D6/P3.6 38 AD7/D7/P3.7 37 A8m/A0/P2 ...
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... CP1+ 2 CP0- 3 CP0+ 4 AGND 5 AV+ 6 VREF 7 VREF0 8 AIN0.0 9 AIN0.1 10 AIN0.2 11 AIN0.3 12 AIN0.4 13 AIN0.5 14 AIN0.6 15 AIN0.7 16 Figure 4.5. C8051F131/3 Pinout Diagram (TQFP-64) C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 C8051F131 C8051F133 Rev. 1.4 48 /WR/P0.7 47 AD0/D0/P3.0 46 AD1/D1/P3.1 45 AD2/D2/P3.2 44 AD3/D3/P3.3 43 AD4/D4/P3.4 42 AD5/D5/P3.5 41 VDD 40 DGND 39 AD6/D6/P3.6 38 AD7/D7/P3.7 37 A8m/A0/P2.0 36 A9m/A1/P2.1 35 A10m/A2/P2.2 34 A11m/A3/P2 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2 PIN 1 DESIGNATOR Figure 4.6. TQFP-64 Package Drawing Rev. 1.4 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0. 12. 10. 0. 12. 10. 0.45 0.60 0.75 ...
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... The PGA amplifies the AMUX output signal by an amount deter- mined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (SFR Definition 5.3). The PGA can be software-programmed for gains of 0. 16. Gain defaults to unity on reset. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 ADC0LTH ADC0LTL AV+ ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 The Temperature Sensor transfer function is shown in Figure 5.2. The output voltage (V input when the Temperature Sensor is selected by bits AMX0AD3-0 in register AMX0SL; this voltage will be amplified by the PGA according to the user-programmed PGA settings. Typical values for the Slope and Offset parameters can be found in Table 5.1. ...
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... Step 4. Process ADC0 data. When CNVSTR0 is used as a conversion start source, it must be enabled in the crossbar, and the corre- sponding pin must be set to open-drain, high-impedance mode (see page 235 for more details on Port I/O configuration). C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Section “18. Port Input/Output” on Rev. 1.4 57 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 5.2.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR0 signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR0 is low ...
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... ADC resolution in bits (12). Differential Mode MUX Select AIN0 MUX Input MUX SAMPLE C AIN0 MUX MUX Select Figure 5.4. ADC0 Equivalent Input Circuits C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 TOTAL n 2 ------ - = TOTAL SAMPLE SA Single-Ended Mode MUX Select AIN0.x = 10pF SAMPLE ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 5.1. AMX0CF: AMUX0 Configuration 0 SFR Page: 0xBA SFR Address: R/W R/W R Bit7 Bit6 Bit5 Bits7–4: UNUSED. Read = 0000b; Write = don’t care. Bit3: AIN67IC: AIN0.6, AIN0.7 Input Pair Configuration Bit. 0: AIN0.6 and AIN0.7 are independent single-ended inputs. ...
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... AIN0.2 +(AIN0.0) 1101 AIN0.2 –(AIN0.1) +(AIN0.2) 1110 AIN0.0 AIN0.1 –(AIN0.3) +(AIN0.0) +(AIN0.2) 1111 –(AIN0.1) –(AIN0.3) C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W - AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 00000000 Bit4 Bit3 Bit2 Bit1 AMX0AD3–0 0011 0100 0101 0110 AIN0.3 AIN0 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 5.3. ADC0CF: ADC0 Configuration 0 SFR Page: 0xBC SFR Address: R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. The SAR Conversion clock is derived from system clock by the following equation, where ...
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... ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. Bit0: AD0LJST: ADC0 Left Justify Select. 0: Data in ADC0H:ADC0L registers are right-justified. 1: Data in ADC0H:ADC0L registers are left-justified. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W AD0WINT Bit4 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 5.5. ADC0H: ADC0 Data Word MSB 0 SFR Page: 0xBF SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–4 are the sign extension of Bit3. Bits 3–0 are the upper 4 bits of the 12-bit ADC0 Data Word. For AD0LJST = 1: Bits 7– ...
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... For AD0LJST = 0: Gain n -------------- - Code = Vin 2 ; ‘n’ for Single-Ended; ‘n’=11 for Differential. VREF Figure 5.5. ADC0 Data Word Example C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 ADC0H:ADC0L (AD0LJST = 1) 0xFFF0 0x8000 0x7FF0 0x0000 ADC0H:ADC0L (AD0LJST = 1) 0x7FF0 0x4000 0x0010 0x0000 0xFFF0 0xC000 0x8000 Rev ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 5.3. ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times ...
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... SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte 0 SFR Page: 0xC6 SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Low byte of ADC0 Less-Than Data Word. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Input Voltage ADC Data (AD0.0 - AGND) Word REF x (4095/4096) 0x0FFF AD0WINT not affected 0x0201 REF x (512/4096) 0x0200 ADC0LTH:ADC0LTL 0x01FF AD0WINT=1 0x0101 REF x (256/4096) 0x0100 ADC0GTH:ADC0GTL 0x00FF AD0WINT not affected 0x0000 0 Given: AMX0SL = 0x00, AMX0CF = 0x00 AD0LJST = ‘0’, ADC0LTH:ADC0LTL = 0x0200, ADC0GTH:ADC0GTL = 0x0100 ...
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... ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x0100 and > 0xFFFF. (In 2s-complement math, 0xFFFF = -1.) Figure 5.7. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Input Voltage ADC Data (AD0.0 - AD0.1) Word REF x (2047/2048) 0x07FF ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Input Voltage ADC Data (AD0.0 - AGND) Word REF x (4095/4096) 0xFFF0 AD0WINT not affected 0x2010 REF x (512/4096) 0x2000 ADC0LTH:ADC0LTL 0x1FF0 AD0WINT=1 0x1010 REF x (256/4096) 0x1000 ADC0GTH:ADC0GTL 0x0FF0 AD0WINT not affected 0x0000 0 Given: AMX0SL = 0x00, AMX0CF = 0x00, AD0LJST = ‘1’, ADC0LTH:ADC0LTL = 0x2000, ADC0GTH:ADC0GTL = 0x1000 ...
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... ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x1000 and > 0xFFF0. (2s-complement math.) Figure 5.9. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Input Voltage ADC Data (AD0.0 - AD0.1) Word REF x (2047/2048) 0x7FF0 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F120/1/4/ 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified. DD Parameter Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Differential mode Offset Temperature Coefficient ...
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... The PGA amplifies the AMUX output signal by an amount deter- mined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (SFR Definition 6.3). The PGA can be software-programmed for gains of 0. 16. Gain defaults to unity on reset. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Section “9. Voltage Reference” on page 113 ADC0LTH ADC0LTL ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 The Temperature Sensor transfer function is shown in Figure 6.2. The output voltage (V input when the Temperature Sensor is selected by bits AMX0AD3-0 in register AMX0SL; this voltage will be amplified by the PGA according to the user-programmed PGA settings. Typical values for the Slope and Offset parameters can be found in Table 6.1. ...
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... Step 4. Process ADC0 data. When CNVSTR0 is used as a conversion start source, it must be enabled in the crossbar, and the corre- sponding pin must be set to open-drain, high-impedance mode (see page 235 for more details on Port I/O configuration). C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Section “18. Port Input/Output” on Rev. 1.4 75 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 6.2.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR0 signal is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR0 is low ...
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... ADC resolution in bits (10). Differential Mode MUX Select AIN0 MUX Input MUX SAMPLE C AIN0 MUX MUX Select Figure 6.4. ADC0 Equivalent Input Circuits C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 TOTAL n 2 ------ - = TOTAL SAMPLE SA Single-Ended Mode MUX Select AIN0.x = 10pF SAMPLE ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 6.1. AMX0CF: AMUX0 Configuration 0 SFR Page: 0xBA SFR Address: R/W R/W R Bit7 Bit6 Bit5 Bits7–4: UNUSED. Read = 0000b; Write = don’t care. Bit3: AIN67IC: AIN0.6, AIN0.7 Input Pair Configuration Bit. 0: AIN0.6 and AIN0.7 are independent single-ended inputs. ...
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... AIN0.1 AIN0.2 +(AIN0.0) 1101 AIN0.2 –(AIN0.1) +(AIN0.2) 1110 AIN0.0 AIN0.1 –(AIN0.3) +(AIN0.0) +(AIN0.2) 1111 –(AIN0.1) –(AIN0.3) C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W - AMX0AD3 AMX0AD2 AMX0AD1 AMX0AD0 00000000 Bit4 Bit3 Bit2 Bit1 AMX0AD3-0 0011 0100 0101 0110 AIN0.3 AIN0 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 6.3. ADC0CF: ADC0 Configuration 0 SFR Page: 0xBC SFR Address: R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where ...
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... ADC0 Window Comparison Data match has not occurred since this flag was last cleared. 1: ADC0 Window Comparison Data match has occurred. Bit0: AD0LJST: ADC0 Left Justify Select. 0: Data in ADC0H:ADC0L registers are right-justified. 1: Data in ADC0H:ADC0L registers are left-justified. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W AD0WINT Bit4 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 6.5. ADC0H: ADC0 Data Word MSB 0 SFR Page: 0xBF SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7–4 are the sign extension of Bit3. Bits 3–0 are the upper 4 bits of the 10-bit ADC0 Data Word. For AD0LJST = 1: Bits 7– ...
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... For AD0LJST = 0: Gain n -------------- - Code = Vin 2 ; ‘n’ for Single-Ended; ‘n’= 9 for Differential. VREF Figure 6.5. ADC0 Data Word Example C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 ADC0H:ADC0L (AD0LJST = 1) 0xFFC0 0x8000 0x7FC0 0x0000 ADC0H:ADC0L (AD0LJST = 1) 0x7FC0 0x4000 0x0040 0x0000 0xFFC0 0xC000 0x8000 Rev ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 6.3. ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times ...
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... SFR Definition 6.10. ADC0LTL: ADC0 Less-Than Data Low Byte 0 SFR Page: 0xC6 SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Low byte of ADC0 Less-Than Data Word. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W ...
Page 86
... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Input Voltage ADC Data (AD0.0 - AGND) Word REF x (1023/1024) 0x03FF ADWINT not affected 0x0201 REF x (512/1024) 0x0200 ADC0LTH:ADC0LTL 0x01FF ADWINT=1 0x0101 REF x (256/1024) 0x0100 ADC0GTH:ADC0GTL 0x00FF ADWINT not affected 0x0000 0 Given: AMX0SL = 0x00, AMX0CF = 0x00 AD0LJST = ‘0’, ADC0LTH:ADC0LTL = 0x0200, ADC0GTH:ADC0GTL = 0x0100 ...
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... ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x0100 and > 0xFFFF. (In 2s-complement math, 0xFFFF = -1.) Figure 6.7. 10-Bit ADC0 Window Interrupt Example: Right Justified Differential C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Input Voltage ADC Data (AD0.0 - AD0.1) Word REF x (511/512) 0x01FF ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Input Voltage ADC Data (AD0.0 - AGND) Word REF x (1023/1024) 0xFFC0 ADWINT not affected 0x8040 REF x (512/1024) 0x8000 ADC0LTH:ADC0LTL 0x7FC0 ADWINT=1 0x4040 REF x (256/1024) 0x4000 ADC0GTH:ADC0GTL 0x3FC0 ADWINT not affected 0x0000 0 Given: AMX0SL = 0x00, AMX0CF = 0x00, AD0LJST = ‘1’, ADC0LTH:ADC0LTL = 0x2000, ADC0GTH:ADC0GTL = 0x1000 ...
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... ADC0 Window Compare Interrupt (AD0WINT = ‘1’) if the resulting ADC0 Data Word is < 0x2000 and > 0xFFC0. (2s-complement math.) Figure 6.9. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Input Voltage ADC Data (AD0.0 - AD0.1) Word REF x (511/512) 0x7FC0 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 6.1. 10-Bit ADC0 Electrical Characteristics (C8051F122/3/6/7 and C8051F13x 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified. DD Parameter Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Differential mode Offset Temperature Coefficient ...
Page 91
... ADC2 inputs. To configure an AIN2 pin for analog input, set to ‘0’ the corresponding bit in register P1MDIN. Port 1 pins selected as analog inputs are skipped by the Digital I/O Crossbar. See “18.1.5. Configuring Port 1 Pins as Analog Inputs” on page 240 the AIN2 pins. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Section “9. Voltage Reference” on ADC2GTH ADC2LTH AV+ ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 7.2. ADC2 Modes of Operation ADC2 has a maximum conversion speed of 500 ksps. The ADC2 conversion clock (SAR2 clock divided version of the system clock, determined by the AD2SC bits in the ADC2CF register. The maximum ADC2 conversion clock is 6 MHz. 7.2.1. Starting a Conversion A conversion can be initiated in one of five ways, depending on the programmed states of the ADC2 Start of Conversion Mode bits (AD2CM2-0) in ADC2CN ...
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... Write '1' to AD2BUSY, Timer 3 Overflow, Timer 2 Overflow, Write '1' to AD0BUSY (AD2CM[2:0]=000, 001, 011, 1xx) SAR Clocks Low Power AD2TM=1 or Convert SAR Clocks Track or AD2TM=0 Convert Figure 7.2. ADC2 Track and Conversion Example Timing C8051F120/1/2/3/4/5/6/7 C8051F130/1/2 Track Convert Low Power Mode Convert 1 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 7.2.3. Settling Time Requirements A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the ADC2 MUX resistance, the ADC2 sampling capacitance, any external source resis- tance, and the accuracy required for the conversion. Figure 7.3 shows the equivalent ADC2 input circuit. ...
Page 95
... PIN01IC: AIN2.0, AIN2.1 Input Pair Configuration Bit. 0: AIN2.0 and AIN2.1 are independent single-ended inputs. 1: AIN2.0 and AIN2.1 are (respectively) +, – differential input pair. Note: The ADC2 Data Word is in 2’s complement format for channels configured as differential. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W - ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 7.2. AMX2SL: AMUX2 Channel Select 2 SFR Page: 0xBB SFR Address: R/W R/W R Bit7 Bit6 Bit5 Bits7–3: UNUSED. Read = 00000b; Write = don’t care. Bits2–0: AMX2AD2–0: AMX2 Address Bits. 000-111b: ADC Inputs selected per chart below. ...
Page 97
... CLK SAR2 Bit2: UNUSED. Read = 0b; Write = don’t care. Bits1–0: AMP2GN1–0: ADC2 Internal Amplifier Gain (PGA). 00: Gain = 0.5 01: Gain = 1 10: Gain = 2 11: Gain = 4 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W AD2SC1 AD2SC0 - AMP2GN1 AMP2GN0 11111000 Bit4 Bit3 Bit2 SAR2 Rev. 1.4 ...
Page 98
... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 7.4. ADC2CN: ADC2 Control 2 SFR Page: 0xE8 (bit addressable) SFR Address: R/W R/W R/W AD2EN AD2TM AD2INT AD2BUSY AD2CM2 AD2CM1 Bit7 Bit6 Bit5 Bit7: AD2EN: ADC2 Enable Bit. 0: ADC2 Disabled. ADC2 is in low-power shutdown. 1: ADC2 Enabled. ADC2 is active and ready for data conversions. ...
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... VREF * (64/128) 0 –VREF * (64/128) 0xC0 (-64d) –VREF * (128/128) 0x80 (-128d) Gain ------------------------ - Code = Vin REF 2 V Figure 7.4. ADC2 Data Word Example C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W Bit4 Bit3 Bit2 ADC2 0xFF 0x80 0x40 0x00 256 ADC2 0x7F 0x40 0x00 ...
Page 100
... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 7.3. ADC2 Programmable Window Detector The ADC2 Programmable Window Detector continuously compares the ADC2 output to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an inter- rupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. ...
Page 101
... REF x (-1/256) 0xFF (-1d) ADC2GT 0xFE (-2d) AD2WINT not affected 0x80 (-128d) -REF Figure 7.6. ADC2 Window Compare Examples, Differential Mode C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 ADC2 Input Voltage (AIN2.x - AIN2.y) REF x (127/128) 0x7F (127d) 0x11 (17d) REF x (16/128) 0x10 (16d) 0x0F (15d) AD2WINT=1 0x00 (0d) ...
Page 102
... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 7.6. ADC2GT: ADC2 Greater-Than Data Byte 2 SFR Page: 0xC4 SFR Address: R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: ADC2 Greater-Than Data Word. SFR Definition 7.7. ADC2LT: ADC2 Less-Than Data Byte 2 SFR Page: 0xC6 SFR Address: R/W ...
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... SAR Clock Frequency Conversion Time in SAR Clocks Track/Hold Acquisition Time Throughput Rate Input Voltage Range Input Capacitance Power Supply Current Operating Mode, 500 ksps (AV+ supplied to ADC2) Power Supply Rejection C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Conditions Min DC Accuracy — — — 0.5±0.3 — –1±0.2 — ...
Page 104
... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2 OTES 104 Rev. 1.4 ...
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... DAC0MD1 DAC0MD0 DAC0DF2 DAC0DF1 DAC0DF0 8 8 DAC1EN DAC1MD1 DAC1MD0 DAC1DF2 DAC1DF1 DAC1DF0 8 8 Figure 8.1. DAC Functional Block Diagram C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 for more information on configuring the voltage reference for the REF 8 12 DAC0 8 REF 8 12 DAC1 8 Rev. 1.4 Section AV+ DAC0 AGND ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 8.1.1. Update Output On-Demand In its default mode (DAC0CN.[4:3] = ‘00’) the DAC0 output is updated “on-demand” write to the high- byte of the DAC0 data register (DAC0H important to note that writes to DAC0L are held, and have no effect on the DAC0 output until a write to DAC0H takes place. If writing a full 12-bit word to the DAC data registers, the 12-bit data word is written to the low byte (DAC0L) and high byte (DAC0H) data registers ...
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... Bits7–0: DAC0 Data Word Most Significant Byte. SFR Definition 8.2. DAC0L: DAC0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: DAC0 Data Word Least Significant Byte. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 8.3. DAC0CN: DAC0 Control R/W R/W R/W DAC0EN - - Bit7 Bit6 Bit5 Bit7: DAC0EN: DAC0 Enable Bit. 0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode. 1: DAC0 Enabled. DAC0 Output pin is active; DAC0 is operational. Bits6–5: UNUSED. Read = 00b; Write = don’t care. ...
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... Bits7–0: DAC1 Data Word Most Significant Byte. SFR Definition 8.5. DAC1L: DAC1 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: DAC1 Data Word Least Significant Byte. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 8.6. DAC1CN: DAC1 Control R/W R/W R/W DAC1EN - - Bit7 Bit6 Bit5 Bit7: DAC1EN: DAC1 Enable Bit. 0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode. 1: DAC1 Enabled. DAC1 Output pin is active; DAC1 is operational. Bits6–5: UNUSED. Read = 00b; Write = don’t care. ...
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... Output Voltage Swing Startup Time code L Load Regulation 0xFFF Power Consumption (each DAC) Power Supply Current (AV+ Data Word = 0x7FF supplied to DAC) C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Conditions Min Static Performance — — — — — — — — — — ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2 OTES 112 Rev. 1.4 ...
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... ADC and the two DACs to reference an external voltage reference or the on-chip voltage reference output (with an external connection). ADC0 may also reference the DAC0 output internally, and ADC2 may reference the analog power supply voltage, via the VREF multiplexers shown in Figure 9.1. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 113 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 VDD External R1 Voltage Reference Circuit DGND + 4.7F 0.1F Recommended Bypass Capacitors Figure 9.1. Voltage Reference Functional Block Diagram (C8051F120/2/4/6) SFR Definition 9.1. REF0CN: Reference Control (C8051F120/2/4/6) 0 SFR Page: 0xD1 SFR Address: R/W R/W R Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. ...
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... VREF multiplexers shown in Figure 9.2. VDD External R1 Voltage Reference Circuit DGND + 4.7F 0.1F Recommended Bypass Capacitors Figure 9.2. Voltage Reference Functional Block Diagram (C8051F121/3/5/7) C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 REF0CN AV VREFA 0 1 DAC0 Ref DAC1 BIASE VREF x2 Band-Gap REFBE Rev ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 9.2. REF0CN: Reference Control (C8051F121/3/5/7) 0 SFR Page: 0xD1 SFR Address: R/W R/W R Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bit4: AD0VRS: ADC0 Voltage Reference Select. 0: ADC0 voltage reference from VREFA pin. 1: ADC0 voltage reference from DAC0 output. ...
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... Reference Configuration on the C8051F130/1/2/3 On the C8051F130/1/2/3 devices, the VREF0 pin provides a voltage reference input for ADC0, which can be connected to an external precision reference or the internal voltage reference, as shown in Figure 9.3. The REF0CN register for the C8051F130/1/2/3 is described in SFR Definition 9.3. ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 9.1. Voltage Reference Electrical Characteristics V = 3.0 V, AV+ = 3.0 V, –40 to +85 °C unless otherwise specified. DD Parameter Analog Bias Generator Power BIASE = 1 Supply Current Output Voltage 25 °C ambient VREF Short-Circuit Current VREF Temperature Coefficient Load Regulation Load = 0 to 200 µA to AGND 4.7 µ ...
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... CP1RIE CP1FIE CP1MD1 CP1MD0 CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 CP1+ CP1- Figure 10.1. Comparator Functional Block Diagram C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Section “18.1. Ports 0 through 3 and the for Crossbar and port initialization details. CP0MD AV+ Reset Decision Tree + SET CLR (SYNCHRONIZER) ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Comparator interrupts can be generated on rising-edge and/or falling-edge output transitions. (For inter- rupt enable and priority control, see set upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set upon the Comparator0 rising- edge interrupt. Once set, these bits remain set until cleared by software. The Output State of Comparator0 can be obtained at any time by reading the CP0OUT bit ...
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... Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Positive Hysteresis Figure 10.2. Comparator Hysteresis Plot C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 OUT (Programmed by CP0HYN Bits) Negative Hysteresis Maximum Disabled Negative Hysteresis Maximum Rev. 1.4 Negative Hysteresis Voltage 121 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 10.1. CPT0CN: Comparator0 Control 1 SFR Page: 0x88 SFR Address: R/W R/W R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. ...
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... Bits3–2: UNUSED. Read = 00b, Write = don’t care. Bits1–0: CP0MD1–CP0MD0: Comparator0 Mode Select These bits select the response time for Comparator0. Mode CP0MD1 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W CP0FIE - - CP0MD1 CP0MD0 00000010 Bit4 Bit3 Bit2 CP0MD0 Notes 0 Fastest Response Time 1 — ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 10.3. CPT1CN: Comparator1 Control 2 SFR Page: 0x88 SFR Address: R/W R/W R/W CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1–. ...
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... Bits3–2: UNUSED. Read = 00b, Write = don’t care. Bits1–0: CP1MD1–CP1MD0: Comparator1 Mode Select These bits select the response time for Comparator1. Mode CP0MD1 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W CP1FIE - - CP1MD1 CP1MD0 00000010 Bit4 Bit3 Bit2 CP0MD0 Notes 0 Fastest Response Time 1 — ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 10.1. Comparator Electrical Characteristics V = 3.0 V, AV+ = 3.0 V, –40 to +85 °C unless otherwise specified. DD Parameter Response Time: * Mode 1 Response Time: * Mode 1 Response Time: * Mode 1 Response Time: * Mode 1 Common-Mode Rejection Ratio Positive Hysteresis 1 Positive Hysteresis 2 Positive Hysteresis 3 Positive Hysteresis 4 Negative Hysteresis 1 ...
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... With the CIP-51's system clock running at 100 MHz, it has a peak throughput of 100 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 Number of Instructions 26 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Section 23 ), two full-duplex UARTs (see description in Section 25 ), and interfaces directly with the MCU’s - Extended Interrupt Handler - ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 ACCUMULATOR PSW DATA POINTER PC INCREMENTER PROGRAM COUNTER (PC) PRGM. ADDRESS REG. CONTROL RESET LOGIC CLOCK STOP POWER CONTROL IDLE Figure 11.1. CIP-51 Block Diagram Programming and Debugging Support A JTAG-based serial interface is provided for in-system programming of the Flash program memory and communication with on-chip debug support logic ...
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... Subtract indirect RAM from A with borrow SUBB A, #data Subtract immediate from A with borrow INC A Increment A INC Rn Increment register INC direct Increment direct byte INC @Ri Increment indirect RAM C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 ). The External Memory Interface provides a fast for details. Arithmetic Operations Rev. 1.4 Section Clock Bytes Cycles ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 11.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description DEC A Decrement A DEC Rn Decrement register DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A and B DIV AB Divide Decimal adjust A ANL A, Rn AND Register to A ...
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... Long subroutine call RET Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect relative to DPTR C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Boolean Manipulation Program Branching Rev. 1.4 Clock Bytes Cycles ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 11.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description JZ rel Jump if A equals zero JNZ rel Jump if A does not equal zero CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel Compare immediate to A and jump if not equal ...
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... Program Memory The C8051F12x and C8051F130/1 have a 128 kB program memory space. The MCU implements this pro- gram memory space as in-system re-programmable Flash memory in four 32 kB code banks. A common code bank (Bank always accessible from addresses 0x0000 to 0x7FFF. The three upper code banks (Bank 1, Bank 2, and Bank 3) are each mapped to addresses 0x8000 to 0xFFFF, depending on the selection of bits in the PSBANK register, as described in SFR Definition 11 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 11.1. PSBANK: Program Space Bank Select R/W R/W R COBANK Bit7 Bit6 Bit5 Bits 7 – 6: Reserved. Bits 5 – 4: COBANK: Constant Operations Bank Select. These bits select which Flash bank is targeted during constant operations (MOVC and Flash MOVX) involving addresses 0x8000 to 0xFFFF. These bits are ignored when accessing the ...
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... The MCUs also have built-in hardware for a stack record which is accessed by the debug logic. The stack record is a 32-bit shift register, where each PUSH or increment SP pushes one record bit onto the register, and each CALL pushes two record bits onto the register. (A POP or decrement SP pops one record bit, C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 135 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 and a RET pops two record bits, also.) The stack record circuitry can also detect an overflow or underflow on the 32-bit shift register, and can notify the debug software even with the MCU running at speed. 11.2.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFR’ ...
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... PAGES) ” designation. For example, the Port I/O registers P0, P1, P2, and P3 all have the “ (ALL PAGES) ” designation, indicating these SFR’s are accessible from all SFR pages regardless of the SFRPAGE regis- ter value. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFRPGCN Bit SFRPAGE SFRNEXT SFRLAST Rev ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 11.2.6.3.SFR Page Stack Example The following is an example that shows the operation of the SFR Page Stack during interrupts. In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51 is executing in-line code that is writing values to Port 5 (SFR “P5”, located at address 0xD8 on SFR Page 0x0F) ...
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... SFR Page 0x0F for Port 5) is pushed down to the SFRLAST register, the “bottom” of the stack. Note that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be overwritten. See Figure 11.7 below. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Page 0x02 Automatically pushed on stack in ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFRPAGE pushed to SFRNEXT SFRNEXT pushed to SFRLAST Figure 11.7. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR On exit from the PCA interrupt service routine, the CIP-51 will return to the ADC2 Window Comparator ISR. On execution of the RETI instruction, SFR Page 0x00 used to access the PCA registers will be auto- matically popped off of the SFR Page Stack, and the contents of the SFRNEXT register will be moved to the SFRPAGE register. Software in the ADC2 ISR can continue to access SFR’ ...
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... RETI instruction). The automatic switching of the SFRPAGE and operation of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFRPGCN). See SFR Definition 11.2. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Page 0x02 Automatically popped off of the ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 11.2. SFRPGCN: SFR Page Control R/W R/W R Bit7 Bit6 Bit5 Bits7–1: Reserved. Bit0: SFRPGEN: SFR Automatic Page Control Enable. Upon interrupt, the C8051 Core will vector to the specified interrupt service routine and auto- matically switch the SFR page to the corresponding peripheral or function’s SFR page. This bit is used to control this autopaging function ...
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... Write: Sets the SFR Page in the last entry of the SFR Stack. This will cause the SFRNEXT SFR to have this SFR page value upon a return from interrupt. Read: Returns the value of the SFR page contained in the last entry of the SFR stack. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 11.2. Special Function Register (SFR) Memory Map 0(8) 1(9) 0 SPI0CN PCA0L PCA0H (ALL 3 PAGES ADC0CN PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 PCA0CPL4 PCA0CPH4 ADC2CN PCA0CPL5 PCA0CPH5 1 ACC E0 2 (ALL 3 PAGES) F XBR0 0 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPM5 1 D8 ...
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... CPT1CN CPT1MD 3 F FLSTAT PLL0CN OSCICN (ALL (ALL 3 PAGES) PAGES) PAGES) F 0(8) 1(9) C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 AMX0SL ADC0CF AMX2SL ADC2CF P1MDIN EMI0CF CCH0LC P0MDOUT P1MDOUT SPI0DAT SPI0CKR P4MDOUT P5MDOUT MAC0ACC0 MAC0ACC1 MAC0ACC2 MAC0ACC3 TL0 TL1 TH0 OSCICL OSCXCN PLL0DIV DPL DPH SFRPAGE ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 11.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. SFR Register Address Page ACC 0xE0 All Pages Accumulator ADC0CF 0xBC 0 ADC0CN 0xE8 0 ADC0GTH 0xC5 0 ADC0GTL 0xC4 0 ADC0H 0xBF 0 ADC0L 0xBE 0 ADC0LTH 0xC7 ...
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... F P4MDOUT 0x9C F P5 0xD8 F P5MDOUT 0x9D F C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Description EMIF Configuration EMIF Control EMIF Timing Control Flash Access Limit Flash Scale Flash Status MAC0 Accumulator Byte 0 (LSB) MAC0 Accumulator Byte 1 MAC0 Accumulator Byte 2 MAC0 Accumulator Byte 3 (MSB) MAC0 A Register High Byte ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 11.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. SFR Register Address Page P6 0xE8 F P6MDOUT 0x9E F P7 0xF8 F P7MDOUT 0x9F F PCA0CN 0xD8 0 PCA0CPH0 0xFC 0 PCA0CPH1 0xFE 0 PCA0CPH2 0xEA 0 PCA0CPH3 0xEC 0 PCA0CPH4 ...
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... TMR3L 0xCC 1 TMR4CF 0xC9 2 TMR4CN 0xC8 2 TMR4H 0xCD 2 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Description Voltage Reference Control Reset Source UART 0 Slave Address UART 0 Slave Address Mask UART 0 Data Buffer UART 1 Data Buffer UART 0 Control UART 1 Control SFR Page Control SMBus Slave Address SMBus Control ...
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... Refers to a register in the C8051F120/1/4/5 only. 2. Refers to a register in the C8051F122/3/6/7 and C8051F130/1/2/3 only. 3. Refers to a register in the C8051F120/1/2/3/4/5/6/7 only. 4. Refers to a register in the C8051F120/1/2/3 and C8051F130/1/2/3 only. 5. Refers to a register in the C8051F120/2/4/6 only. 6. Refers to a register in the C8051F121/3/5/7 only. 7. Refers to a register in the C8051F130/1/2/3 only. ...
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... R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed XRAM and Flash memory. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 11.9. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into (addition borrow from (subtraction) the high order nibble ...
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... SFR Definition 11.11 Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7– Register. This register serves as a second accumulator for certain arithmetic operations. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W ACC.4 ACC.3 ACC.2 ACC.1 Bit4 Bit3 Bit2 R/W R/W ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 11.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 20 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt- pending flag(s) located in an SFR ...
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... Serial Peripheral Interface 0x0033 SMBus Interface 0x003B ADC0 Window Comparator 0x0043 Programmable Counter 0x004B Array Comparator 0 Falling Edge 0x0053 Comparator 0 Rising Edge 0x005B Comparator 1 Falling Edge 0x0063 C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Priority Pending Flags Order Top None N/A N IE0 (TCON. TF0 (TCON.5) ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 11.4. Interrupt Summary (Continued) Interru Interrupt Source pt Vector Comparator 1 Rising Edge 0x006B Timer 3 0x0073 ADC0 End of Conversion 0x007B Timer 4 0x0083 ADC2 Window Comparator 0x008B ADC2 End of Conversion 0x0093 RESERVED 0x009B UART1 0x00A3 11.3.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior- ity interrupt service routine can be preempted by a high priority interrupt ...
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... This bit sets the masking of the Timer 0 interrupt. 0: Disable Timer 0 interrupts. 1: Enable Timer 0 interrupts. Bit0: EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable External Interrupt 0. 1: Enable External Interrupt 0. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W ES0 ET1 EX1 ET0 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 11.13. IP: Interrupt Priority R/W R/W R PT2 Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: Timer 2 interrupt set to low priority. 1: Timer 2 interrupt set to high priority. ...
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... This bit sets the masking of the SMBus interrupt. 0: Disable SMBus interrupts. 1: Enable SMBus interrupts. Bit0: ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt. This bit sets the masking of SPI0 interrupt. 0: Disable SPI0 interrupts. 1: Enable SPI0 interrupts. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W ECP0F EPCA0 EWADC0 ESMB0 Bit4 ...
Page 160
... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 11.15. EIE2: Extended Interrupt Enable 2 R/W R/W R/W - ES1 - Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b, Write = don't care. Bit6: ES1: Enable UART1 Interrupt. This bit sets the masking of the UART1 interrupt. 0: Disable UART1 interrupts. 1: Enable UART1 interrupts. ...
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... SMBus interrupt set to high priority. Bit0: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority. 1: SPI0 interrupt set to high priority. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W PCP0F PPCA0 PWADC0 PSMB0 ...
Page 162
... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 11.17. EIP2: Extended Interrupt Priority 2 R/W R/W R/W - PS1 - Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b, Write = don't care. Bit6: ES1: UART1 Interrupt Priority Control. This bit sets the priority of the UART1 interrupt. 0: UART1 interrupt set to low priority. ...
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... IDLE bit, the CPU may not wake from IDLE mode when a future interrupt occurs. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 All internal registers and memory maintain their original Section 13 for more information on the use and con- Rev ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 11.4.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes. In Stop mode, the CPU and oscillators are stopped, effectively shutting down all digital peripherals. Each analog peripheral must be shut down individually prior to entering Stop Mode ...
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... Multiply And Accumulate (MAC0) The C8051F120/1/2/3 and C8051F130/1/2/3 devices include a multiply and accumulate engine which can be used to speed up many mathematical operations. MAC0 contains a 16-by-16 bit multiplier and a 40-bit adder, which can perform integer or fractional multiply-accumulate and multiply operations on signed input values in two SYSCLK cycles. A rounding engine provides a rounded 16-bit fractional result after an addi- tional (third) SYSCLK cycle ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 12.2. Integer and Fractional Math MAC0 is capable of interpreting the 16-bit inputs stored in MAC0A and MAC0B as signed integers or as signed fractional numbers. When the MAC0FM bit (MAC0CF.1) is cleared to ‘0’, the inputs are treated as 16-bit, 2’s complement, integer values. After the operation, the accumulator will contain a 40-bit, 2’s com- plement, integer value ...
Page 167
... When the MAC0SD bit is set to ‘1’, the MAC0 accumulator will shift right. Right-shift operations are sign-extended with the current value of bit 39. Note that the status flags in the MAC0STA register are not affected by shift operations. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Accumulator Rounded Results Results Available ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 12.6. Rounding and Saturation A Rounding Engine is included, which can be used to provide a rounded result when operating on frac- tional numbers. MAC0 uses an unbiased rounding algorithm to round the data stored in bits 31 – the accumulator, as shown in Table 12.1. Rounding occurs during the third stage of the MAC0 pipeline, after any shift operation write to the LSB of the accumulator ...
Page 169
... The rounding register is updated after this instruction MOV MAC0CF, #30h ; Initiate a Right-shift MOV MAC0CF, #30h ; Initiate a second Right-shift NOP ; After this instruction, the accumulator should be 0xE044221108 NOP ; The rounding register is updated after this instruction C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 4660 – 292 = – 1360720 Rev. 1.4 169 ...
Page 170
... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 12.1. MAC0CF: MAC0 Configuration MAC0SC MAC0SD MAC0CA MAC0SAT MAC0FM MAC0MS 00000000 Bit7 Bit6 Bit5 Bits 7 – 6: UNUSED: Read = 00b, Write = don’t care. Bit 5: MAC0SC: Accumulator Shift Control. When set to 1, the 40-bit MAC0 Accumulator register will be shifted during the next SYSCLK cycle. The direction of the shift (left or right) is controlled by the MAC0RS bit. This bit is cleared to ‘ ...
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... The contents of this register should not be changed by software during the first two MAC0 pipeline stages. SFR Definition 12.3. MAC0AH: MAC0 A High Byte Bit7 Bit6 Bit5 Bits 7 – 0: High Byte (bits 15 – MAC0 A Register. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R R/W R/W R/W - MAC0HO MAC0Z MAC0SO Bit4 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 12.4. MAC0AL: MAC0 A Low Byte Bit7 Bit6 Bit5 Bits 7 – 0: Low Byte (bits 7 – MAC0 A Register. SFR Definition 12.5. MAC0BH: MAC0 B High Byte Bit7 Bit6 Bit5 Bits 7 – 0: High Byte (bits 15 – MAC0 B Register. SFR Definition 12.6. MAC0BL: MAC0 B Low Byte ...
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... The contents of this register should not be changed by software during the first two MAC0 pipeline stages. SFR Definition 12.9. MAC0ACC1: MAC0 Accumulator Byte Bit7 Bit6 Bit5 Bits 7 – 0: Byte 1 (bits 15 – MAC0 Accumulator. *Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2 Bit4 Bit3 Bit2 Bit1 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 12.10. MAC0ACC0: MAC0 Accumulator Byte Bit7 Bit6 Bit5 Bits 7 – 0: Byte 0 (bits 7 – MAC0 Accumulator. *Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages. SFR Definition 12.11. MAC0OVR: MAC0 Accumulator Overflow ...
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... SFR Definition 12.13. MAC0RNDL: MAC0 Rounding Register Low Byte Bit7 Bit6 Bit5 Bits 7 – 0: Low Byte (bits 7 – MAC0 Rounding Register. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2 Bit4 Bit3 Bit2 Bit1 Rev. 1.4 R Reset Value 00000000 Bit0 SFR Address: 0xCE SFR Page: 3 175 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 176 Rev. 1.4 ...
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... Comparator0 CP0 CP0- enable) Internal Clock Generator PLL Circuitry XTAL1 OSC XTAL2 Figure 13.1. Reset Sources C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 14. Oscillators 13.7. Watchdog Timer Reset ” on page VDD Supply Monitor Supply + Reset - Timeout (CP0 reset Missing WDT Clock Detector (one- ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 13.1. Power-on Reset The C8051F120/1/2/3/4/5/6/7 family incorporates a power supply monitor that holds the MCU in the reset state until V rises above the V DD RST to Table 13.1 for the Electrical Characteristics of the power supply monitor circuit. The RST pin is asserted low until the end of the 100 ms V ...
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... The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the period between specific writes to its control register. If this period exceeds the programmed limit, a WDT C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 14. Oscillators ” on page 185 ) enables the Missing Clock Detector. ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN) shown in SFR Definition 13.1. 13.7.1. Enable/Reset WDT The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's applica- tion software should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow ...
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... Reading the WDTCN.[4] bit indicates the Watchdog Timer Status. 0: WDT is inactive 1: WDT is active Bits2 – 0: Watchdog Timeout Interval Bits The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits, WDTCN.7 must be set to 0. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W Bit4 Bit3 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 13.2. RSTSRC: Reset Source R R/W R/W - CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF Bit7 Bit6 Bit5 Bit7: Reserved. Bit6: CNVRSEF: Convert Start 0 Reset Source Enable and Flag Write: 0: CNVSTR0 is not a reset source. 1: CNVSTR0 is a reset source (active low). Read: 0: Source of prior reset was not CNVSTR0 ...
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... AV+ for RST Output Valid V POR Threshold ( RST Minimum RST Low Time to Gen- erate a System Reset Reset Time Delay Missing Clock Detector Timeout *Note: When operating at frequencies above 50 MHz, minimum C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Conditions I = 8.5 mA 2 RST = 0.0 V RST rising edge after V DD crosses V ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2 OTES 184 Rev. 1.4 ...
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... Internal Calibrated Oscillator All devices include a calibrated internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 14.1. OSCICL is factory calibrated to obtain a 24.5 MHz frequency. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 OSCICL OSCICN AV+ EN ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Electrical specifications for the precision internal oscillator are given in Table 14.1. Note that the system clock may be derived from the programmed internal oscillator divided defined by the IFCN bits in register OSCICN. SFR Definition 14.1. OSCICL: Internal Oscillator Calibration. R/W R/W ...
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... XTLVLD. RC and C modes typically require no startup time. The PLL also requires time to lock onto the desired frequency, and the PLL Lock Flag (PLLLCK in register PLL0CN) is set to ‘1’ by hardware once the PLL is locked on the correct frequency. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 187 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 14.3. CLKSEL: System Clock Selection R/W R/W R CLKDIV1 CLKDIV0 Bit7 Bit6 Bit5 Bits 7–6: Reserved. Bits 5–4: CLKDIV1–0: Output SYSCLK Divide Factor. These bits can be used to pre-divide SYSCLK before it is output to a port pin through the crossbar ...
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... R = Pullup resistor value in k C MODE (Circuit from Figure 14.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired where frequency of oscillation in MHz C = capacitor value on XTAL1, XTAL2 pins Power Supply on MCU in Volts DD C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R R/W R/W - XFCN2 XFCN1 Bit4 Bit3 Bit2 Bit1 RC (XOSCMD = 10x) f ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 14.4. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in SFR Definition 14.4 (OSCXCN register). For example ...
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... PLLLCK bit (PLL0CN.5) will be set to a ‘1’. The resulting PLL frequency will be set accord- ing to the equation: Where “Reference Frequency” is the selected source clock frequency, PLLN is the PLL Multiplier, and PLLM is the PLL Pre-divider. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 PLL0CN PLL0FLT Divided 0 Reference ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 PLL Frequency 14.7.3. Powering on and Initializing the PLL To set up and use the PLL as the system clock after power-up of the device, the following procedure should be implemented: Step 1. Ensure that the reference clock to be used (internal or external) is running and stable. Step 2. Set the PLLSRC bit (PLL0CN.2) to select the desired clock source for the PLL. ...
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... PLLEN: PLL Enable Bit. 0: PLL is held in reset. 1: PLL is enabled. PLLPWR must be ‘1’. Bit 0: PLLPWR: PLL Power Enable. 0: PLL bias generator is de-activated. No static power is consumed. 1: PLL bias generator is active. Must be set for PLL to operate. C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R R/W R/W PLLLCK 0 PLLSRC PLLEN ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 SFR Definition 14.6. PLL0DIV: PLL Pre-divider R/W R/W R Bit7 Bit6 Bit5 Bits 7–5: UNUSED: Read = 000b; Write = don’t care. Bits 4–0: PLLM4–0: PLL Reference Clock Pre-divider. These bits select the pre-divide value of the PLL reference clock. When set to any non-zero value, the reference clock will be divided by the value in PLLM4– ...
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... MHz Table 14.2. PLL Frequency Characteristics –40 to +85 °C unless otherwise specified Parameter Input Frequency (Divided Reference Frequency) PLL Output Frequency *Note: The maximum operating frequency of the C8051F124/5/6 MHz C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 R/W R/W R/W R/W PLLLP3 PLLLP2 PLLLP1 Bit4 Bit3 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 14.3. PLL Lock Timing Characteristics –40 to +85 °C unless otherwise specified Input Multiplier Frequency (Pll0mul MHz MHz 196 Pll0flt Output Min Setting Frequency 0x0F 100 MHz 0x0F 65 MHz 0x1F 80 MHz 0x1F 45 MHz 0x2F 60 MHz 0x2F 30 MHz 0x3F 50 MHz ...
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... N : OTES C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Rev. 1.4 197 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 198 Rev. 1.4 ...
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... Flash Memory All devices include either 128 kB (C8051F12x and C8051F130/ (C8051F132/3) of on-chip, reprogrammable Flash memory for program code or non-volatile data storage. An additional 256-byte page of Flash is also included for non-volatile data storage. The Flash memory can be programmed in-sys- tem through the JTAG interface software using the MOVX write instructions. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1 ...
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... C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Table 15.1. Flash Electrical Characteristics V = 2.7 to 3.6 V; –40 to +85 °C DD Parameter 1 C8051F12x and C8051F130/1 Flash Size 1 C8051F132/3 Flash Size Endurance Erase Cycle Time Write Cycle Time Notes: 1. Includes 256-byte Scratch Pad Area 2. 1024 Bytes at location 0x1FC00 to 0x1FFFF are reserved. ...