C8051F130 Silicon Laboratories Inc, C8051F130 Datasheet - Page 166
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C8051F130
Manufacturer Part Number
C8051F130
Description
IC 8051 MCU 128K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F130
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1147
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12.2. Integer and Fractional Math
MAC0 is capable of interpreting the 16-bit inputs stored in MAC0A and MAC0B as signed integers or as
signed fractional numbers. When the MAC0FM bit (MAC0CF.1) is cleared to ‘0’, the inputs are treated as
16-bit, 2’s complement, integer values. After the operation, the accumulator will contain a 40-bit, 2’s com-
plement, integer value. Figure 12.2 shows how integers are stored in the SFRs.
When the MAC0FM bit is set to ‘1’, the inputs are treated at 16-bit, 2’s complement, fractional values. The
decimal point is located between bits 15 and 14 of the data word. After the operation, the accumulator will
contain a 40-bit, 2’s complement, fractional value, with the decimal point located between bits 31 and 30.
Figure 12.3 shows how fractional numbers are stored in the SFRs.
166
-(2
-(2
* The MAC0RND register contains the 16 LSBs of a two's complement number. The MAC0N Flag can be
used to determine the sign of the MAC0RND register.
-(2
* -2
-1
15
39
8
)
)
)
2
2
2
2
14
38
1
-1
7
MAC0OVR
MAC0OVR
2
2
2
13
-1
-2
Figure 12.3. Fractional Mode Data Representation
High Byte
High Byte
2
2
2
Figure 12.2. Integer Mode Data Representation
-2
12
-3
2
2
33
High Byte
2
2
2
2
-3
11
-4
2
2
32
MAC0A, and MAC0B Bit Weighting
MAC0A and MAC0B Bit Weighting
1
2
MAC0 Accumulator Bit Weighting
MAC0 Accumulator Bit Weighting
2
-4
2
10
-5
2
MAC0RND Bit Weighting
2
2
31
MAC0ACC3 : MAC0ACC2 : MAC0ACC1 : MAC0ACC0
MAC0ACC3 : MAC0ACC2 : MAC0ACC1 : MAC0ACC0
0
-5
2
2
-6
9
2
2
2
30
-1
-6
2
2
Rev. 1.4
-7
8
2
2
2
-7
29
-2
2
2
-8
7
2
2
2
28
-8
-3
2
2
-9
6
2
-9
2
2
-10
5
2
-10
Low Byte
Low Byte
2
2
2
2
-11
-27
Low Byte
4
4
2
-11
2
2
2
2
-12
-28
2
3
3
-12
2
2
2
2
2
-13
-29
2
2
-13
2
2
2
2
2
-14
-30
-14
1
1
2
2
2
2
2
-15
-31
-15
0
0
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