XC68HC705B32CFN Freescale Semiconductor, XC68HC705B32CFN Datasheet - Page 294

• Manufacturer Part Number: XC68HC705B32CFN
• Description: IC MCU 2.1MHZ 32K OTP 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC68HC705B32CFN

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pulse length modulation registers
Q
QFP
R
R8 – Receive data bit 8
RAM
RDI
RDRF – Receive data register full flag
RE – receiver enable
receive data in
receiver
register outline
registers
RESET
reset timing diagram
resets
RIE – receiver interrupt enable
ROM
RTIM – Reset time
RVU
RWAT – Watchdog after reset
RWU – receiver wake-up
S
SBK – Send break
SCI
SCI interrupts
SCI registers
SCP1, SCP0 – Serial prescaler select bits
SCR2, SCR1, SCR0 – SCI rate select bits
SCT2, SCT1, SCT0 – SCI rate select bits
SDIP
SEC – Secure bit
self-check mode
self-check ROM
serial bootstrap
Serial communications control register 1
Freescale
viii
PLMA, PLMB
block diagram
receiver
sampling technique
synchronous transmission
transmitter
two-wire system
BAUD
SCCR1
SCCR2
SCDR
SCSR
CPHA
CPOL
6–6
12–2
13–2
3–1
3–1
12–3
9–1
9–3, E–5, F–5
6–3
3–1
6–12
6–18
6–16
6–12
6–10
6–10
6–14
6–3
9–10
6–6
3–8
6–3
E–16
3–2
A–5
E–9
5–11
6–15
6–2
C–7
9–1
6–1
6–15
,
,
F–9
6–11
6–7
E–8
6–15
,
,
H–12
C–7
6–14
6–9
F–8
,
E–8
6–16
6–10
,
6–18
6–18
6–19
F–8
INDEX
Serial communications control register 2
Serial communications data register
Serial communications status register
serial RAM loader
SFA – Slow or fast mode selection for PLMA
SFB – Slow or fast mode selection for PLMB
single chip mode
SLOW
SM – Slow mode
SM – slow mode selection bit
start bit detection
STOP
T
T8 – transmit data bit 8
TC – Transmit complete flag
TCIE – Transmit complete interrupt enable
TDO
TDRE – Transmit data register empty flag
TE – Transmitter enable
TIE – Transmit interrupt enable
Timer control register
timer interrupts
timer state diagrams
Timer status register
TOF – Timer overflow status flag
TOIE – Timer overflow interrupt enable
transmit data out
LBCL
M
R8
T8
WAKE
ILIE
RE
RIE
RWU
SBK
TCIE
TE
TIE
FE
IDLE
NF
OR
RDRF
TC
TDRE
IEDG1
OCIE
OLV1
OLV2
TOIE
ICF1
ICF2
OCF1
OCF2
TOF
6–8
2–6
6–11
2–9
6–11
6–16
6–11
6–14
6–17
6–17
6–15
6–17
6–14
6–14
6–14
6–15
5–6
5–6
5–7
6–14
6–16
5–4
6–15
,
5–4
6–13
5–5
5–5
5–6
5–7
6–16
6–16
6–11
5–5
3–7
9–10
,
2–1
6–8
3–10
6–6
5–12
2–2
5–12
,
,
,
6–11
F–16
7–3
6–14
6–21
6–16
,
2–9
,
H–19
6–14
7–4
5–6
,
6–10
8–6
5–4
MC68HC05B6
,
6–16
6–14
9–4
3–10
3–10
,
,
7–3
7–3