MC56F8323VFB60 Freescale Semiconductor, MC56F8323VFB60 Datasheet - Page 75

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MC56F8323VFB60

Manufacturer Part Number
MC56F8323VFB60
Description
IC MPU HYBRID DSP 32K 64-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheet

Specifications of MC56F8323VFB60

Core Processor
56800
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, SCI, SPI
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
27
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.25 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
For Use With
MC56F8323EVME - BOARD EVALUATION MC56F8323
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC56F8323VFB60
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
5.6.10.4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.10.5
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
5.6.10.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.10.7
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
5.6.10.8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.11
5.6.11.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Freescale Semiconductor
Preliminary
Base + $A
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
RESET
Write
Read
Vector Base Address Register (VBA)
Reserved—Bits 9–8
ADC A Zero Crossing or Limit Error Interrupt Priority Level
(ADCA_ZC IPL)—Bits 7–6
Reserved—Bits 5–4
ADC A Conversion Complete Interrupt Priority Level
(ADCA_CC IPL)—Bits 3–2
Reserved—Bits 1–0
Reserved—Bits 15–13
15
0
0
Figure 5-13 Vector Base Address Register (VBA)
14
0
0
13
0
0
12
0
56F8323 Technical Data, Rev. 17
11
0
10
0
9
0
8
0
VECTOR BASE ADDRESS
7
0
6
0
5
0
4
0
3
0
2
0
Register Descriptions
1
0
0
0
75

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