MC56F8323VFB60 Freescale Semiconductor, MC56F8323VFB60 Datasheet - Page 23
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MC56F8323VFB60
Manufacturer Part Number
MC56F8323VFB60
Description
IC MPU HYBRID DSP 32K 64-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheet
1.MC56F8123VFBE.pdf
(140 pages)
Specifications of MC56F8323VFB60
Core Processor
56800
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, SCI, SPI
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
27
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.25 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-LQFP
For Use With
MC56F8323EVME - BOARD EVALUATION MC56F8323
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC56F8323VFB60
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Preliminary
Signal Name
(prescaler_
(GPIOB4)
(GPIOB3)
(GPIOB2)
HOME0
SCLK0
MOSI0
clock)
(TA3)
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Pin No.
49
25
24
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Output
Output
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Input/
Input/
Type
Input
State During
disabled,
pull-up is
output is
In reset,
enabled
enabled
enabled
pull-up
pull-up
Reset
56F8323 Technical Data, Rev. 17
Input,
Input,
Home — Quadrature Decoder 0, HOME input
TA3 — Timer A, Channel 3
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Clock Output - can be used to monitor the internal prescaler_clock
signal (see
In the 56F8323, the default state after reset is HOME0.
In the 56F8123, the default state is not one of the functions offered
and must be reconfigured.
SPI 0 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. A Schmitt trigger input is used for noise
immunity.
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCLK0.
SPI 0 Master Out/Slave In — This serial data pin is an output from a
master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is MOSI0.
Part 6.5.7
CLKO Select Register, SIM_CLKOSR).
Signal Description
Signal Pins
23
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