MC68HC908GR16VFJ Freescale Semiconductor, MC68HC908GR16VFJ Datasheet - Page 161

• Manufacturer Part Number: MC68HC908GR16VFJ
• Description: IC MCU 16K FLASH 8MHZ SPI 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR16VFJ

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.8.1 ESCI Control Register 1
ESCI control register 1 (SCC1):
LOOPS — Loop Mode Select Bit
ENSCI — Enable ESCI Bit
TXINV — Transmit Inversion Bit
M — Mode (Character Length) Bit
Freescale Semiconductor
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This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the
ESCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver
must be enabled to use loop mode. Reset clears the LOOPS bit.
This read/write bit enables the ESCI and the ESCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in ESCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit.
This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit.
This read/write bit determines whether ESCI characters are eight or nine bits long (See
14-5).The ninth bit can serve as a receiver wakeup signal or as a parity bit. Reset clears the M bit.
1 = Loop mode enabled
0 = Normal operation enabled
1 = ESCI enabled
0 = ESCI disabled
1 = Transmitter output inverted
0 = Transmitter output not inverted
1 = 9-bit ESCI characters
0 = 8-bit ESCI characters
ESCI prescaler register, SCPSC
ESCI arbiter control register, SCIACTL
ESCI arbiter data register, SCIADAT
Enables loop mode operation
Enables the ESCI
Controls output polarity
Controls character length
Controls ESCI wakeup method
Controls idle character detection
Enables parity function
Controls parity type
Address: $0013
Setting the TXINV bit inverts all transmitted values including idle, break,
start, and stop bits.
Reset:
Read:
Write:
LOOPS
Bit 7
0
Figure 14-10. ESCI Control Register 1 (SCC1)
ENSCI
6
0
MC68HC908GR16 Data Sheet, Rev. 5.0
TXINV
5
0
NOTE
M
4
0
WAKE
3
0
ILTY
2
0
PEN
1
0
Bit 0
PTY
0
Table
I/O Registers
161