MC68HC908GR16VFJ Freescale Semiconductor, MC68HC908GR16VFJ Datasheet - Page 118

• Manufacturer Part Number: MC68HC908GR16VFJ
• Description: IC MCU 16K FLASH 8MHZ SPI 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR16VFJ

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Low-Voltage Inhibit (LVI)
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See
5-2. Configuration Register 1 (CONFIG1)
occurs, the MCU remains in reset until V
reset. See
LVI. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
11.3.1 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at 0 to enable the LVI module, and
the LVIRSTD bit must be at 1 to disable LVI resets.
11.3.2 Forced Reset Operation
In applications that require V
module to reset the MCU when V
LVIPWRD and LVIRSTD bits must be at 0 to enable the LVI module and to enable LVI resets.
118
Addr.
$FE0C
Register Name
15.3.2.5 Low-Voltage Inhibit (LVI) Reset
LVI Status Register
See page 119.
FROM CONFIG1
DETECTOR
(LVISR)
LOW V
LVI5OR3
V
DD
DD
Reset:
Read:
Write:
DD
Figure 11-1. LVI Module Block Diagram
Figure 11-2. LVI I/O Register Summary
to remain above the V
V
V
DD
DD
DD
LVIOUT
FROM CONFIG
> LVI
£ LVI
Bit 7
MC68HC908GR16 Data Sheet, Rev. 5.0
DD
LVIPWRD
falls below the V
0
Trip
Trip
levels below the V
DD
= 1
= 0
for details of the LVI’s configuration bits. Once an LVI reset
= Unimplemented
rises above a voltage, V
6
0
0
LVIOUT
for details of the interaction between the SIM and the
TRIPF
TRIPF
5
0
0
STOP INSTRUCTION
FROM CONFIG1
TRIPF
level. In the configuration register, the
LVIRSTD
level, enabling LVI resets allows the LVI
level, software can monitor V
4
0
0
TRIPR
3
0
0
, which causes the MCU to exit
FROM CONFIG1
LVISTOP
LVI RESET
2
0
0
Freescale Semiconductor
1
0
0
DD
by polling
Figure
Bit 0
0
0