MC68HC908LJ12CFU Freescale Semiconductor, MC68HC908LJ12CFU Datasheet - Page 379

• Manufacturer Part Number: MC68HC908LJ12CFU
• Description: IC MCU 12K FLASH 8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908LJ12CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MC68HC908LJ12
Freescale Semiconductor
NOTE:
NOTE:
—
Rev. 2.1
The LVI trip point selection bits, LVISEL[1:0], select the trip point
voltage, V
trip points are shown in
Setting LVI interrupt enable bit, LVIIE, enables LVI interrupts whenever
the LVIOUT bit toggles (from logic 0 to logic 1, or from logic 1 to logic 0).
After a power-on reset (POR) the user must configure the LVISEL[1:0}
bits for 3.3V or 5V operation before enabling the LVI module (by clearing
the LVIPWRD bit in CONFIG1 register).
If the user requires 3.3V mode and enables the LVI module after
configuring the LVISEL[1;0] bits to 3.3V operation mode while the V
supply is not above the V
go into reset. The LVI in this case will hold the MCU in reset until either
V
reset or V
power-on reset.
LVISTOP, LVIPWRD, LVIRSTD, and LVISEL[1:0] are in the
configuration registers. See
(CONFIG)
occurs, the MCU remains in reset until V
V
Inhibit (LVI) Reset
LVI. The output of the comparator controls the state of the LVIOUT flag
in the LVI status register (LVISR). The LVIIE, LVIIF, and LVIIAK bits in
the LVISR control LVI interrupt functions.
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
DD
TRIPR
goes above the rising 3.3V trip point, V
, which causes the MCU to exit reset. See
DD
TRIPF
for details of the LVI’s configuration bits. Once an LVI reset
decreases to approximately 0V which will re-trigger the
Low-Voltage Inhibit (LVI)
, to be configured for 5V or 3.3V operation. The actual
for details of the interaction between the SIM and the
Section 23. Electrical
TRIPF
Section 5. Configuration Registers
for 3.3V mode, the MCU will immediately
DD
TRIPR
rises above a voltage,
Specifications.
, which will release
9.4.2.5 Low-Voltage
Low-Voltage Inhibit (LVI)
Technical Data
DD
379