MC68HC908LJ12CFU Freescale Semiconductor, MC68HC908LJ12CFU Datasheet - Page 139

no-image

MC68HC908LJ12CFU

Manufacturer Part Number
MC68HC908LJ12CFU
Description
IC MCU 12K FLASH 8MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908LJ12CFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908LJ12CFU
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC908LJ12CFU
Manufacturer:
MOT
Quantity:
80
Part Number:
MC68HC908LJ12CFU
Manufacturer:
FRE/MOT
Quantity:
20 000
Part Number:
MC68HC908LJ12CFUE
Manufacturer:
FREESCALE
Quantity:
5 588
9.4.2.2 Computer Operating Properly (COP) Reset
MC68HC908LJ12
Freescale Semiconductor
CGMOUT
PORRST
OSC1
IRST
ICLK
RST
IAB
Rev. 2.1
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12 through 5
of the SIM counter. The SIM counter output, which occurs at least every
2
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at V
while the MCU is in monitor mode. The COP module can be disabled
only through combinational logic conditioned with the high voltage signal
on the RST or the IRQ pin. This prevents the COP from becoming
disabled as a result of external noise. During a break state, V
RST pin disables the COP module.
13
CYCLES
4096
– 2
4
ICLK cycles, drives the COP counter. The COP should be
Figure 9-7. POR Recovery
System Integration Module (SIM)
CYCLES
32
CYCLES
32
System Integration Module (SIM)
$FFFE
$FFFF
Technical Data
TST
on the
TST
139

Related parts for MC68HC908LJ12CFU