MC68HC908LJ12CFU Freescale Semiconductor, MC68HC908LJ12CFU Datasheet - Page 254

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MC68HC908LJ12CFU

Manufacturer Part Number
MC68HC908LJ12CFU
Description
IC MCU 12K FLASH 8MHZ 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908LJ12CFU

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Infrared Serial Communications
Technical Data
254
Address:
Infrared Serial Communications Interface Module (IRSCI)
SCTIE — SCI Transmit Interrupt Enable Bit
TCIE — Transmission Complete Interrupt Enable Bit
SCRIE — SCI Receive Interrupt Enable Bit
ILIE — Idle Line Interrupt Enable Bit
TE — Transmitter Enable Bit
Reset:
Read:
Write:
This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests. Reset clears the SCTIE bit.
This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests. Reset clears the SCRIE bit.
This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the idle condition
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
SCTIE
$0014
Bit 7
0
Figure 13-13. SCI Control Register 2 (SCC2)
TCIE
6
0
SCRIE
5
0
ILIE
4
0
TE
3
0
MC68HC908LJ12
RE
Freescale Semiconductor
2
0
RWU
1
0
Rev. 2.1
Bit 0
SBK
0

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