MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 49

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Chapter 6
Operating Modes
6.1 Introduction
This section describes the operation of the device with respect to the oscillator source and the low-power
modes:
6.2 Oscillator Source
The microcontroller unit (MCU) can be clocked by either an internal low-power oscillator (LPO) without
external components or by an external pin oscillator (EPO) which uses external components. The enable
and selection of the clock source is determined by the state of the oscillator select bits (OM1 and OM2)
in the interrupt status and control register (ISCR) as shown in
IRQE — External Interrupt Request Enable Bit
OM1 and OM2 — Oscillator Select Bits
Freescale Semiconductor
•
•
•
•
This read/write bit enables external interrupts. Refer to
These bits control the selection and enabling of the oscillator source for the MCU. One choice is the
internal LPO and the other oscillator is the EPO which is common to most M68HC05 MCU devices.
The EPO uses external components like filter capacitors and a crystal or ceramic resonator and
consumes more power than the LPO. The selection and enable conditions for these two oscillators are
shown in
Therefore, the lowest power is consumed when OM1 is cleared. The state with both OM1 and OM2
set is provided so that the EPO can be started up and allowed to stabilize while the LPO still clocks the
MCU.
Stop mode
Wait mode
Halt mode
Data-retention mode
Table
Address:
Reset:
Read:
Write:
6-1. Reset clears OM1 and sets OM2, which selects the LPO and disables the EPO.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
$000D
IRQE
Bit 7
Figure 6-1. IRQ Status and Control Register (ISCR)
1
= Unimplemented
OM2
6
1
OM1
5
0
R
4
0
0
Chapter 4 Interrupts
IRQF
R
3
0
Figure
= Reserved
6-1.
2
0
0
IRQR
1
0
0
for more details.
Bit 0
0
0
49