MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 23

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Freescale Semiconductor
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
Addr.
$000A
$000B
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Core Timer Status and Control
Core Timer Counter Register
Analog Multiplex Register
Data Direction Register C
Data Direction Register A
Data Direction Register B
Register
Port C
SIOP Control Register
SIOP Status Register
Port A Data Register
Port B Data Register
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Register (CTSCR)
(1)
Unimplemented
See page 102.
See page 103.
Data Register
See page 55.
See page 58.
See page 67.
See page 73.
See page 56.
See page 59.
See page 67.
See page 97.
See page 99.
(PORTC)
(PORTA)
(PORTB)
Figure 2-3. Register Summary (Sheet 1 of 3)
(AMUX)
(DDRC)
(DDRA)
(DDRB)
(CTCR)
(SCR)
(SSR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
DDRC7
DDRB7
HOLD
Bit 7
CTOF
SPIE
SPIF
Bit 7
PB7
PC7
0
1
0
0
0
0
0
0
0
0
= Unimplemented
DHOLD
DDRC6
DDRB6
DCOL
RTIF
SPE
PB6
PC6
6
0
0
0
0
0
0
0
6
0
0
0
DDRA5
DDRB5
DDRC5
CTOFE
LSBF
PC5
PA5
PB5
INV
5
0
0
0
0
0
5
0
0
0
0
Unaffected by reset
Unaffected by reset
Unaffected by reset
DDRA4
DDRB4
DDRC4
MSTR
VREF
RTIE
PC4
PA4
PB4
4
R
0
0
0
0
0
4
0
0
0
0
= Reserved
DDRA3
DDRB3
DDRC3
CTOFR
MUX4
SPIR
PA3
PB3
PC3
3
0
0
0
0
0
0
3
0
0
0
0
0
DDRA2
DDRB2
DDRC2
RTIFR
MUX3
CPHA
PA2
PB2
PC2
U = Unaffected
2
0
0
0
0
0
0
2
0
0
0
0
Input/Output Registers
DDRC1
DDRA1
DDRB1
MUX2
SPR1
PA1
PB1
PC1
RT1
1
0
0
0
0
1
1
0
0
0
0
DDRC0
DDRA0
DDRB0
MUX1
Bit 0
SPR0
Bit 0
PA0
PB0
PC0
RT0
0
0
0
0
1
0
0
0
0
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