MC68HC705JP7CDW Freescale Semiconductor, MC68HC705JP7CDW Datasheet - Page 108

• Manufacturer Part Number: MC68HC705JP7CDW
• Description: IC MCU 8BIT 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705JP7CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 22
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Programmable Timer
When the free-running counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) is set in
the TSR. When the TOF is set, it can generate an interrupt if the timer overflow interrupt enable bit (TOIE)
is also set in the TCR. The TOF flag bit can only be reset by reading the TMRL after reading the TSR.
Other than clearing any possible TOF flags, reading the TMRH and TMRL in any order or any number of
times does not have any effect on the 16-bit free-running counter.
11.3 Alternate Counter Registers
The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is
shown in
any reads of the alternate counter will not have any effect on the TOF flag bit and timer interrupts. The
alternate counter registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
The alternate counter registers (ACRH and ACRL) shown in
contain the current high and low bytes of the 16-bit free-running counter. Writing to the alternate counter
registers has no effect. Reset of the device presets the timer counter to $FFFC.
The ACRL latch is a transparent read of the LSB until a read of the ACRH takes place. A read of the ACRH
latches the LSB into the ACRL location until the ACRL is again read. The latched value remains fixed even
108
Figure
Address:
Address:
RESET
To prevent interrupts from occurring between readings of the TMRH and
TMRL, set the I bit in the condition code register (CCR) before reading
TMRH and clear the I bit after reading TMRL.
READ
ACRH
Reset:
Reset:
Read:
Read:
Write:
Write:
11-4. The alternate counter registers behave the same as the timer registers, except that
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Figure 11-5. Alternate Counter Registers (ACRH and ACRL)
$001A
$001B
Bit 15
Bit 7
Bit 7
Bit 7
1
1
$FFFC
READ
Figure 11-4. Alternate Counter Block Diagram
= Unimplemented
14
6
1
6
6
1
ACRH ($001A)
13
LATCH
5
1
5
5
1
16-BIT COUNTER
NOTE
12
4
1
4
4
1
ACRL ($001B)
TMR LSB
11
Figure 11-5
3
1
3
3
1
10
2
1
2
2
1
÷ 4
are read-only locations which
1
9
1
1
1
0
Freescale Semiconductor
INTERNAL
INTERNAL
(OSC ÷ 2)
READ
ACRL
CLOCK
DATA
BUS
Bit 0
Bit 8
Bit 0
Bit 0
1
0