MC912DT128ACPV Freescale Semiconductor, MC912DT128ACPV Datasheet - Page 39
MC912DT128ACPV
Manufacturer Part Number
MC912DT128ACPV
Description
IC 8MHZ 16 BIT MICROCONTROLLER
Manufacturer
Freescale Semiconductor
Series
HC12r
Datasheet
1.MC912DG128ACPVER.pdf
(478 pages)
Specifications of MC912DT128ACPV
Core Processor
CPU12
Core Size
16-Bit
Speed
8MHz
Connectivity
CAN, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
KMC912DT128ACPV
Q1195202
Q1195202
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC912DT128ACPVE
Manufacturer:
MEANWELL
Quantity:
1 000
Company:
Part Number:
MC912DT128ACPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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2.6 Indexed Addressing Modes
MC68HC912DT128A — Rev 4.0
MOTOROLA
rr0nnnnn
111rr0zs
111rr011
rr1pnnnn
111rr1aa
111rr111
Code (xb)
Postbyte
,r
n,r
[n,r]
n,–r n,+r
A,r
[D,r]
Source Code
n,r
–n,r
–n,r
n,r– n,r+
B,r
D,r
Syntax
The CPU12 indexed modes reduce execution time and eliminate code
size penalties for using the Y index register. CPU12 indexed addressing
uses a postbyte plus zero, one, or two extension bytes after the
instruction opcode. The postbyte and extensions do the following tasks:
Table 2-2. Summary of Indexed Operations
•
•
•
•
Freescale Semiconductor, Inc.
5-bit constant offset n = –16 to +15
Constant offset (9- or 16-bit signed)
16-bit offset indexed-indirect
Auto pre-decrement/increment or Auto post-decrement/increment;
Accumulator offset (unsigned 8-bit or 16-bit)
Accumulator D offset indexed-indirect
For More Information On This Product,
Specify which index register is used.
Determine whether a value in an accumulator is used as an offset.
Enable automatic pre- or post-increment or decrement
Specify use of 5-bit, 9-bit, or 16-bit signed offsets.
rr can specify X, Y, SP, or PC
z-0 = 9-bit with sign in LSB of postbyte(s)
1 = 16-bit
if z = s = 1, 16-bit offset indexed-indirect (see below)
rr can specify X, Y, SP, or PC
rr can specify X, Y, SP, or PC
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
rr can specify X, Y, or SP (PC not a valid choice)
aa-00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
rr can specify X, Y, SP, or PC
Go to: www.freescale.com
Central Processing Unit
Comments
Indexed Addressing Modes
Central Processing Unit
Technical Data
39
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