MC912DT128ACPV Freescale Semiconductor, MC912DT128ACPV Datasheet - Page 187

• Manufacturer Part Number: MC912DT128ACPV
• Description: IC 8MHZ 16 BIT MICROCONTROLLER
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DT128ACPV

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: KMC912DT128ACPV; Q1195202

12.12 Clock Function Registers
RTICTL — Real-Time Interrupt Control Register
MC68HC912DT128A — Rev 4.0
MOTOROLA
RESET:
RTIE
Bit 7
0
RSWAI
6
0
All register addresses shown reflect the reset state. Registers may be
mapped to any 2K byte space.
RTIE — Real Time Interrupt Enable
RSWAI — RTI and COP Stop While in Wait
RSBCK — RTI and COP Stop While in Background Debug Mode
RTBYP — Real Time Interrupt Divider Chain Bypass
Read and write anytime.
Write once in normal modes, anytime in special modes. Read
anytime.
Write once in normal modes, anytime in special modes. Read
anytime.
Write not allowed in normal modes, anytime in special modes. Read
anytime.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = Interrupt requests from RTI are disabled.
1 = Interrupt will be requested whenever RTIF is set.
0 = Allows the RTI and COP to continue running in wait.
1 = Disables both the RTI and COP whenever the part goes into
0 = Allows the RTI and COP to continue running while in
1 = Disables both the RTI and COP when the part is in background
0 = Divider chain functions normally.
1 = Divider chain is bypassed, allows faster testing (the divider
RSBCK
5
0
Wait.
background mode.
mode. This is useful for emulation.
chain is normally XCLK divided by 2
becomes XCLK divided by 4).
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Reserved
Clock Functions
4
0
RTBYP
3
0
RTR2
2
0
RTR1
13
1
0
, when bypassed
Clock Function Registers
RTR0
Bit 0
0
Clock Functions
Technical Data
$0014
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