LH7A400N0G000B5 Sharp Microelectronics, LH7A400N0G000B5 Datasheet - Page 56

• Manufacturer Part Number: LH7A400N0G000B5
• Description: IC ARM9 BLUESTREAK MCU 256PBGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A400N0G000B5

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Data Bus Width: 32 bit
• Data Ram Size: 80 KB
• Maximum Clock Frequency: 250 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

LH7A400
CONTENT REVISIONS
content, causing it to differ from previous versions.
56
8-19-2003
11-15-03
12-07-04
12-13-04
6-21-04
This document contains the following changes to
DATE
PAGE
12-18
18-24
41-42
45-47
41-44
3-11
NO.
ALL
12
39
44
49
34
39
39
54
11
53
50
34
36
37
39
51
36
1
1
2
1
Features
Table 1
Table 3
Table 4
Table 5
Figure 7 and Figure 8 ‘CSx’ added to figures
Figures 11 and 12
Table 10 and
Figure 16
Figures 19-21 and
Printed Circuit Board
Layout Practices
Figure 23
Text
Figure 1
‘Recommended
Operating Conditions’
Table 10
Table 10
Figure 27
Table 1
Figure 26; text
Table 11
Text
Table 7, Figure 6
‘DC Specifications’
Table 8
Table 10
Figure 8 - Figure 11
Text and Figure 23
‘DC Specifications’
PARAGRAPH OR
ILLUSTRATION
Table 12. Record of Revisions
256-ball CABGA package added
CABGA Pins added; VDDA1/VDDA2 combined to VDDA; VSSA1/VSSA2
combined to VSSA
Signal ordering corrected
Table title added to differentiate between PBGA and CABGA packages
CABGA numerical pin list table added
PCDIR signal corrected in PCMCIA timing diagrams
tOSC14 added to both table and figure; XTAL14 added to figure;
tPLLL added to table
Figures and text added
Figure added for CABGA package
Corrected minor text errors; added separate Commercial and Industrial
temperature specification.
Updated to show ALI Interface
Broke out “Commercial” and “Industrial” speed ranges.
Minor corrections to type.
Added ACI timing.
PBGA package drawing added.
Changed names of BOOTWIDTH0 and BOOTWIDTH1 to WIDTH0 and WIDTH1
for consistency with other Sharp SoCs.
Revised text and drawing to indicate that the VSSA pin must be grounded
Added table.
Rolled revision to Version 1.0
Run current corrected to 125 mA and Halt to 25 mA
Added table and accompanying graph for speed/temperature/voltage
Added IRUN, IHALT, and ISTANDBY; corrected IIN.
Corrected values in Table 8.
Changed Asynchronous Memory timing to match SRAM datasheet parameter
naming conventions. Corrected Synchronous Memory times; added synchronous
memory Address Hold time.
Changed Asynchronous Memory timing diagrams to match renamed parameters.
Clarification made to timing for cold boot power-on sequence.
Added IIN without pullup resistors.
Version 1.0
SUMMARY OF CHANGES
32-Bit System-on-Chip
Data Sheet