ATMEGA16-16AUR Atmel, ATMEGA16-16AUR Datasheet - Page 239

• Manufacturer Part Number: ATMEGA16-16AUR
• Description: MCU AVR 128KB FLASH 16MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16-16AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 92. Boundary-scan Signals for the ADC (Continued)
Note:
2466T–AVR–07/10
Signal
Name
MUXEN_2
MUXEN_1
MUXEN_0
NEGSEL_2
NEGSEL_1
NEGSEL_0
PASSEN
PRECH
SCTEST
ST
VCCREN
Incorrect setting of the switches in
choices to the S&H circuitry on the negative input of the output comparator in
from either one ADC pin, Bandgap reference source, or Ground.
Direction as Seen
from the ADC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
If the ADC is not to be used during scan, the recommended input values from
be used. The user is recommended not to use the Differential Gain stages during scan. Switch-
cap based gain stages require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential gain stage is there-
fore not provided.
The AVR ADC is based on the analog circuitry shown in
mation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is
usually to ensure that an applied analog voltage is measured within some limits. This can easily
be done without running a successive approximation algorithm: apply the lower limit on the digi-
tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit
on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following:
•
•
The Port Pin for the ADC channel in use must be configured to be an input with pull-up
disabled to avoid signal contention.
In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before
Description
Input Mux bit 2
Input Mux bit 1
Input Mux bit 0
Input Mux for negative input for
differential signal, bit 2
Input Mux for negative input for
differential signal, bit 1
Input Mux for negative input for
differential signal, bit 0
Enable pass-gate of gain stages.
Precharge output latch of
comparator. (Active low)
Switch-cap TEST enable. Output
from x10 gain stage send out to
Port Pin having ADC_4
Output of gain stages will settle
faster if this signal is high first two
ACLK periods after AMPEN goes
high.
Selects Vcc as the ACC reference
voltage.
Figure 123
will make signal contention and may damage the part. There are several input
Recommended
Input when Not
in Use
0
0
1
0
0
0
1
1
0
0
0
Figure
Figure 123
123. Make sure only one path is selected
Output Values when Recommended
Inputs are used, and CPU is not
Using the ADC
with a successive approxi-
ATmega16(L)
0
0
1
0
0
0
1
1
0
0
0
Table 92
should
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