AT32UC3A0512-ALUR Atmel, AT32UC3A0512-ALUR Datasheet - Page 592
![MCU 32BIT 512KB FLASH 144-LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0512-ALUR
Manufacturer Part Number
AT32UC3A0512-ALUR
Description
MCU 32BIT 512KB FLASH 144-LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUR
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
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Part Number:
AT32UC3A0512-ALUR
Manufacturer:
ATMEL
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30.8.2.18
Offset:
Register Name:
Access Type:
Reset Value:
• HSB_ADDR: HSB Address
This field determines the HSB bus current address of a channel transfer.
The address set on the HSB address bus is HSB_ADDR rounded down to the nearest word-aligned address, i.e.
HSB_ADDR[1:0] is considered as 00b since only word accesses are performed.
Channel HSB start and end addresses may be aligned on any byte boundary.
The software may write this field only when the Channel Enabled bit (CH_EN) of the UDDMAX_STATUS register is clear.
This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB
access byte-width.
The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word
boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel
buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either
determined by the end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFF_CLOSE_IN_EN) is
set.
32058J–AVR32–04/11
31
23
15
0
0
0
7
0
USB Device DMA Channel X HSB Address Register (UDDMAX_ADDR)
30
22
14
0
0
0
6
0
29
21
13
0
0
0
5
0
0x0314 + (X - 1) . 0x10
UDDMAX_ADDR, X in [1..6]
Read/Write
0x00000000
28
20
12
0
0
0
4
0
HSB_ADDR
HSB_ADDR
HSB_ADDR
HSB_ADDR
rwu
rwu
rwu
rwu
27
19
11
0
0
0
3
0
26
18
10
0
0
0
2
0
25
17
0
0
9
0
1
0
AT32UC3A
24
16
0
0
8
0
0
0
592
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