AT32UC3A0512-ALUR Atmel, AT32UC3A0512-ALUR Datasheet - Page 452
![MCU 32BIT 512KB FLASH 144-LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0512-ALUR
Manufacturer Part Number
AT32UC3A0512-ALUR
Description
MCU 32BIT 512KB FLASH 144-LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUR
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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29.6.1.3
29.6.1.4
29.6.1.5
29.6.1.6
32058J–AVR32–04/11
Transmit Buffer List
Address Matching
Interrupts
Transmitting Frames
Transmit data is read from the system memory These buffers are listed in another data structure
that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of
descriptor entries (as defined in
To create this list of buffers:
The MACB register-pair hash address and the four specific address register-pairs must be writ-
ten with the required values. Each register-pair comprises a bottom register and top register,
with the bottom register being written first. The address matching is disabled for a particular reg-
ister-pair after the bottom-register has been written and re-enabled when the top register is
written.
may be written at any time, regardless of whether the receive circuits are enabled or disabled.
There are 14 interrupt conditions that are detected within the MACB. These are ORed to make a
single interrupt. This interrupt is passed to the interrupt controller. On receipt of the interrupt sig-
nal, the CPU enters the interrupt handler. To ascertain which interrupt has been generated, read
the interrupt status register. Note that this register clears itself when read. At reset, all interrupts
are disabled. To enable an interrupt, write to interrupt enable register with the pertinent interrupt
bit set to 1. To disable an interrupt, write to interrupt disable register with the pertinent interrupt
bit set to 1. To check whether an interrupt is enabled or disabled, read interrupt mask register: if
the bit is set to 1, the interrupt is disabled.
To set up a frame for transmission:
1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted
2. Allocate an area 2n words for the transmit buffer descriptor entry in system memory
3. If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap
4. Write address of transmit buffer descriptor entry to MACB register transmit_buffer
5. The transmit circuits can then be enabled by writing to the network control register.
1. Enable transmit in the network control register.
2. Allocate an area of system memory for transmit data. This does not have to be contigu-
3. Set-up the transmit buffer list.
4. Set the network control register to enable transmission and enable interrupts.
5. Write data for transmission into these buffers.
6. Write the address to transmit buffer descriptor queue pointer.
7. Write control and length to word one of the transmit buffer descriptor entry.
8. Write to the transmit start bit in the network control register.
in system memory. Up to 128 buffers per frame are allowed.
and create N entries in this list. Mark all entries in this list as owned by MACB, i.e. bit 31
of word 1 set to 0.
bit — bit 30 in word 1 set to 1.
queue pointer.
ous, varying byte lengths can be used as long as they conclude on byte borders.
See Section “29.5.5” on page 446.
Table 29-2 on page
for details of address matching. Each register-pair
443) that points to this data structure.
AT32UC3A
452
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