AT32UC3A0512-ALUR Atmel, AT32UC3A0512-ALUR Datasheet - Page 497
![MCU 32BIT 512KB FLASH 144-LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
AT32UC3A0512-ALUR
Manufacturer Part Number
AT32UC3A0512-ALUR
Description
MCU 32BIT 512KB FLASH 144-LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUR
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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30. USB On-The-Go Interface (USBB)
30.1
30.2
Table 30-1.
32058J–AVR32–04/11
Pipe/Endpoint
Features
Description
0
1
2
3
4
5
6
Description of USB Pipes/Endpoints
Mnemonic
Rev: 3.1.1.1
•
•
•
•
•
•
•
The Universal Serial Bus (USB) MCU device complies with the Universal Serial Bus (USB) 2.0
specification, but it does NOT feature high-speed USB (480 Mbit/s).
Each pipe/endpoint can be configured in one of several transfer types. It can be associated with
one or more banks of a dual-port RAM used to store the current data payload. If several banks
are used (“ping-pong” mode), then one DPRAM bank is read or written by the CPU or the DMA
while the other is read or written by the USB macro core. This feature is mandatory for isochro-
nous pipes/endpoints.
Table 30-1
PEP0
PEP1
PEP2
PEP3
PEP4
PEP5
PEP6
The theoretical maximal pipe/endpoint configuration (1600 bytes) exceeds the real DPRAM size
(960 bytes). The user needs to be aware of this when configuring pipes/endpoints. To fully use
the 960 bytes of DPRAM, the user could for example use the configuration described in
30-2.
Table 30-2.
USB 2.0 Compliant, Full-/Low-Speed (FS/LS) and On-The-Go (OTG), 12 Mbit/s
7 Pipes/Endpoints
960 bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints
Up to 2 Memory Banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)
Flexible Pipe/Endpoint Configuration and Management with Dedicated DMA Channels
On-Chip Transceivers Including Pull-Ups/Pull-downs.
On-Chip OTG pad including VBUS analog comparator
Pipe/Endpoint
0
1
2
3
describes the hardware configuration of the USB MCU device.
Example of Configuration of Pipes/Endpoints Using the Whole DPRAM
Max. Size
64 bytes
64 bytes
64 bytes
bytes
bytes
bytes
bytes
Mnemonic
PEP0
PEP1
PEP2
PEP3
Max. Nb. Banks
1
64 bytes
64 bytes
64 bytes
64 bytes
Size
DMA
N
Y
Y
Y
Y
Y
Y
Nb. Banks
1
2
2
1
Isochronous/Bulk/Interrupt
Isochronous/Bulk/Interrupt
Isochronous/Bulk/Interrupt
Isochronous/Bulk/Interrupt
Bulk/Interrupt
Bulk/Interrupt
AT32UC3A
Control
Type
Table
497
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