DSPIC30F5015T-20I/PT Microchip Technology, DSPIC30F5015T-20I/PT Datasheet - Page 28

• Manufacturer Part Number: DSPIC30F5015T-20I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015T-20I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• For Use With: AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F
2.5
Concurrent operation of the DSP engine with MCU
instruction flow is not possible, though both the MCU
ALU and DSP engine resources may be used concur-
rently by the same instruction (e.g., ED and EDAC
instructions).
The DSP engine consists of a high speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/
Subtractor (with two target accumulators, round and
saturation logic).
Data input to the DSP engine is derived from one of the
following:
1.
2.
3.
Data output from the DSP engine is written to one of the
following:
1.
2.
3.
DS70082G-page 26
Directly from the W array (registers W4, W5, W6
or W7) via the X and Y data buses for the MAC
class of instructions (MAC, MSC, MPY, MPY.N,
ED, EDAC, CLR and MOVSAC).
From the X bus for all other DSP instructions.
From the X bus for all MCU instructions which
use the barrel shifter.
The target accumulator, as defined by the DSP
instruction being executed.
The X bus for MAC, MSC, CLR and MOVSAC
accumulator writes, where the EA is derived
from W13 only. (MPY, MPY.N, ED and EDAC do
not offer an accumulator write option.)
The X bus for all MCU instructions which use the
barrel shifter.
DSP Engine
Preliminary
The DSP engine also has the capability to perform inher-
ent
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration Register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
7.
A block diagram of the DSP engine is shown in
Figure 2-9.
Note:
Fractional or integer DSP multiply (IF).
Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for AccA (SATA).
Automatic saturation on/off for AccB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator
(ACCSAT).
accumulator-to-accumulator
For CORCON layout, see Table 4-3.
Saturation
 2004 Microchip Technology Inc.
mode
operations,
selection
which