DSPIC30F5015T-20I/PT Microchip Technology, DSPIC30F5015T-20I/PT Datasheet - Page 149

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DSPIC30F5015T-20I/PT

Manufacturer Part Number
DSPIC30F5015T-20I/PT
Description
IC DSPIC MCU/DSP 66K 64TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F5015T-20I/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
For Use With
AC30F008 - MODULE SKT FOR DSPIC30F 64TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F5015T-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
20.7
The module has 3 internal power modes. When the
ADON bit is ‘1’, the module is in Active mode; it is fully
powered and functional. When ADON is ‘0’, the module
is in Off mode. The digital and analog portions of the
circuit are disabled for maximum current savings. In
order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize.
20.8
20.8.1
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the con-
version is aborted. The converter will not continue with
a partially completed conversion on exit from Sleep
mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
The A/D module can operate during Sleep mode if the
A/D clock source is set to RC (ADRC = 1). When the
RC clock source is selected, the A/D module waits one
instruction cycle before starting the conversion. This
allows the SLEEP instruction to be executed, which
eliminates all digital switching noise from the conver-
sion. When the conversion is complete, the CONV bit
will be cleared and the result loaded into the ADCBUF
register.
FIGURE 20-2:
 2004 Microchip Technology Inc.
RAM Contents:
Read to Bus:
Signed Fractional (1.15)
Module Power-down Modes
A/D Operation During CPU Sleep
and Idle Modes
A/D OPERATION DURING CPU
SLEEP MODE
Fractional (1.15)
Signed Integer
Integer
A/D OUTPUT DATA FORMATS
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
Preliminary
0
0
If the A/D interrupt is enabled, the device will wake-up
from Sleep. If the A/D interrupt is not enabled, the A/D
module will then be turned off, although the ADON bit
will remain set.
20.8.2
The ADSIDL bit selects if the module will stop on Idle or
continue on Idle. If ADSIDL = 0, the module will con-
tinue operation on assertion of Idle mode. If ADSIDL =
1, the module will stop on Idle.
20.9
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off, and any
conversion and acquisition sequence is aborted. The
values that are in the ADCBUF registers are not modi-
fied. The A/D result register will contain unknown data
after a Power-on Reset.
20.10 Output Formats
The A/D result is 10-bits wide. The data buffer RAM is
also 10-bits wide. The 10-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
Write data will always be in right justified (integer)
format.
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Effects of a Reset
A/D OPERATION DURING CPU IDLE
MODE
0
0
dsPIC30F
0
0
0
0
DS70082G-page 147
0
0
0
0
0
0

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