DSPIC30F5016-20I/PT Microchip Technology, DSPIC30F5016-20I/PT Datasheet - Page 21
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DSPIC30F5016-20I/PT
Manufacturer Part Number
DSPIC30F5016-20I/PT
Description
IC DSPIC MCU/DSP 66K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F5011T-20IPT.pdf
(34 pages)
3.DSPIC30F6010T-20IPF.pdf
(6 pages)
4.DSPIC30F5016-20IPT.pdf
(100 pages)
Specifications of DSPIC30F5016-20I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
66KB (22K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
For Use With
AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
DSPIC30F501620IPT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F5016-20I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
39. Page 21-9, Register 21-1 I2CCON
Register 21-1:
40. I
TABLE 2:
2004 Microchip Technology Inc.
IFS0<14>
IFS0<13>
IEC0<14>
IEC0<13>
IPC3<10:8>
IPC3<6:4>
Upper Byte:
bit 15
bit 5
Bit Location
I2CEN
R/W-0
in SFR
On page 21-9, Register 21-1: I2CCON: I
Register, the description of the ACKDT bit should
be corrected as follows. All other bit definitions do
not change and hence are not described.
Table 2 below, shows changes to the nomencla-
ture of the I
flag and priority bits. These changes should be
applied to the entire document.
2
C Interrupt Bit Names
Lower Byte:
bit 7
ACKDT: Acknowledge Data bit (When operating as I
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during acknowledge
0 = Send ACK during acknowledge
Legend:
R = Readable
W = Writable
HC = Cleared by Hardware
‘1’ = Bit is set at POR
GCEN
R/W-0
2
U-0
I2CCON: I
C module’s interrupt enable, status
INTERRUPT CONTROLLER
REGISTER MAP: I
NAMES
—
BCLIP<2:0>
I2CIP<2:0>
(Incorrect)
Bit Name
BCLIE
BCLIF
I2CIE
I2CIF
I2CSIDL
2
STREN
R/W-0
R/W-0
C Control Register
(Please read as)
MI2CIP<2:0>
SI2CIP<2:0>
Bit Name
2
MI2CIF
MI2CIE
C BIT
SI2CIF
SI2CIE
SCLREL
dsPIC30F Family Reference Manual
ACKDT
R/W-1
R/W-0
2
HC
C Control
C = Clearable bit
HS = Set by Hardware
‘0’ = Bit cleared at POR
IPMIEN
ACKEN
R/W-0
R/W-0
HC
2
C Master. Applicable during master receive.)
R/W-0
R/W-0
RCEN
A10M
HC
U = Unimplemented bit, read as ‘0’
S = Settable bit
x = Bit is unknown at POR
DISSLW
R/W-0
R/W-0
PEN
HC
R/W-0
SMEN
R/W-0
RSEN
HC
bit 8
DS80169E-page 21
R/W-0
SEN
HC
bit 0