TS80C51RA2-VIA Atmel, TS80C51RA2-VIA Datasheet - Page 72

• Manufacturer Part Number: TS80C51RA2-VIA
• Description: IC MCU 8BIT 256BYTE 40MHZ 40-DIP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of TS80C51RA2-VIA

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40/30MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded V
10.5.15. Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (T
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.
72
(INCLUDES INT0, INT1, TO, T1)
WRITE CYCLE
PORT OPERATION
MOV DEST PORT (P1, P2, P3)
SERIAL PORT SHIFT CLOCK
EXTERNAL PROGRAM MEMORY FETCH
P2 (EXT)
READ CYCLE
INTERNAL
MOV DEST P0
XTAL2
CLOCK
PSEN
ALE
WR
RD
P0
P2
P0
P0
P2
TXD (MODE 0)
SAMPLED
DATA
FLOAT
STATE4
P1
P2
PCL OUT
DPL OR Rt OUT
INDICATES ADDRESS TRANSITIONS
DPL OR Rt OUT
P1
STATE5
P0 PINS SAMPLED
P2
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
OLD DATA
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P1
STATE6
INDICATES DPH OR P2 SFR TO PCH TRANSITION
Figure 33. Clock Waveforms
P2
SAMPLED
FLOAT
DATA
NEW DATA
P1
STATE1
OH
/V
P2
OL
PCL OUT
P1
level occurs. I
STATE2
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
DATA OUT
FLOAT
P2
P1
STATE3
P1, P2, P3 PINS SAMPLED
OL
P2
/I
FLOAT
SAMPLED
OH
DATA
P1
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
STATE4
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
20mA.
P2
Rev. C - 06 March, 2001
PCL OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P1
A
STATE5
P0 PINS SAMPLED
=25 C fully loaded)
P2
RXD SAMPLED