TS80C51RA2-VIA Atmel, TS80C51RA2-VIA Datasheet - Page 47

• Manufacturer Part Number: TS80C51RA2-VIA
• Description: IC MCU 8BIT 256BYTE 40MHZ 40-DIP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of TS80C51RA2-VIA

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40/30MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

WDTPRG Address (0A7h)
Reset value XXXX X000
6.10.2. WDT during Power Down and Idle
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the
user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset
or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power
Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C51Rx2
is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the
WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C51Rx2 while in
Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter
Idle mode.
Rev. C - 06 March, 2001
Bit Number
T4
7
6
5
4
3
2
1
0
7
Mnemonic
Bit
T4
T3
T2
T1
T0
S2
S1
S0
T3
6
Reserved
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
Do not try to set or clear this bit.
S2
0
0
0
0
1
1
1
1
T2
5
S1
0
0
1
1
0
0
1
1
Table 24. WDTPRG Register
S0
0
1
0
1
0
1
0
1
T1
4
Selected Time-out
(2
(2
(2
(2
(2
(2
(2
(2
14
15
16
17
18
19
20
21
- 1) machine cycles, 16.3 ms @ 12 MHz
- 1) machine cycles, 32.7 ms @ 12 MHz
- 1) machine cycles, 65.5 ms @ 12 MHz
- 1) machine cycles, 131 ms @ 12 MHz
- 1) machine cycles, 262 ms @ 12 MHz
- 1) machine cycles, 542 ms @ 12 MHz
- 1) machine cycles, 1.05 s @ 12 MHz
- 1) machine cycles, 2.09 s @ 12 MHz
T0
3
Description
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
S2
2
TS80C51RA2/RD2
S1
1
S0
0
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