TS80C51RA2-VIA Atmel, TS80C51RA2-VIA Datasheet - Page 40

• Manufacturer Part Number: TS80C51RA2-VIA
• Description: IC MCU 8BIT 256BYTE 40MHZ 40-DIP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of TS80C51RA2-VIA

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40/30MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
6.7. Interrupt System
The TS80C51Rx2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts
(timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt. These interrupts are shown in Figure 16.
WARNING: Note that in the first version of RC devices, the PCA interrupt is in the lowest priority. Thus the
order in INT0, TF0, INT1, TF1, RI or TI, TF2 or EXF2, PCA.
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register (See Table 19.). This register also contains a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing
a bit in the Interrupt Priority register (See Table 20.) and in the Interrupt Priority High register (See Table 21.).
shows the bit values and priority levels associated with each combination.
The PCA interrupt vector is located at address 0033H. All other vector addresses are the same as standard C52 devices.
40
EXF2
INT0
INT1
PCA IT
TF0
TF1
TF2
RI
TI
Individual Enable
IE0
IE1
Figure 16. Interrupt Control System
IPH, IP
3
0
3
0
3
0
3
0
3
0
3
0
3
0
Global Disable
High priority
interrupt
Interrupt
polling
sequence, decreasing
from high to low priority
Low priority
interrupt
Rev. C - 06 March, 2001