ATMEGA64-16MJ Atmel, ATMEGA64-16MJ Datasheet - Page 138

• Manufacturer Part Number: ATMEGA64-16MJ
• Description: IC MCU AVR 64K 5V 16MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16MJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TCCR3C –
Timer/Counter3
Control Register C
TCNT1H and TCNT1L
– Timer/Counter1
TCNT3H and TCNT3L
– Timer/Counter3
2490Q–AVR–06/10
• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
• Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate Compare
Match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are imple-
mented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the
effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
• Bit 4:0 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when TCCRnC is written.
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers.
Registers” on page 115.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a Com-
pare Match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the Compare Match on the following timer clock
for all compare units.
Bit
(0x8C)
Read/Write
Initial Value
Bit
0x2D (0x4D)
0x2C (0x4C)
Read/Write
Initial Value
Bit
(0x89)
(0x88)
Read/Write
Initial Value
FOC3A
R/W
R/W
W
7
0
7
0
7
0
FOC3B
R/W
R/W
W
6
0
6
0
6
0
FOC3C
R/W
R/W
W
5
0
5
0
5
0
R/W
R/W
4
–
R
0
4
TCNT1[15:8]
0
4
TCNT3[15:8]
0
TCNT1[7:0]
TCNT3[7:0]
R/W
R/W
R
3
–
0
3
0
3
0
R/W
R/W
R
2
–
0
2
0
2
0
R/W
R/W
R
1
–
0
1
0
1
0
ATmega64(L)
R/W
R/W
R
0
–
0
0
0
0
0
See “Accessing 16-bit
TCCR3C
TCNT1H
TCNT1L
TCNT3H
TCNT3L
138