PIC18LF8520-I/PTG Microchip Technology, PIC18LF8520-I/PTG Datasheet - Page 31

• Manufacturer Part Number: PIC18LF8520-I/PTG
• Description: IC MCU FLASH 16KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8520-I/PTG

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.0
The PIC18FXX20 devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during Sleep and by the
RESET instruction.
FIGURE 3-1:
 2004 Microchip Technology Inc.
MCLR
OSC1
V
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (PBOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
RESET
2: See Table 3-1 for time-out situations.
RC OSC
OST/PWRT
On-chip
Pointer
Stack
PIC18F6520/8520/6620/8620/6720/8720
Brown-out
V
(1)
Module
DD
Detect
WDT
Reset
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET Instruction
Stack Full/Underflow Reset
Rise
OST
PWRT
External Reset
10-bit Ripple Counter
10-bit Ripple Counter
Time-out
Reset
WDT
Power-on Reset
Sleep
BOREN
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 3-2.
These bits are used in software to determine the nature
of the Reset. See Table 3-3 for a full description of the
Reset states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses. The MCLR pin is not driven low by
any internal Resets, including the WDT.
S
R
Enable PWRT
Enable OST
DS39609B-page 29
Q
Chip_Reset
(2)