PIC18LF8520-I/PTG Microchip Technology, PIC18LF8520-I/PTG Datasheet - Page 296

• Manufacturer Part Number: PIC18LF8520-I/PTG
• Description: IC MCU FLASH 16KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8520-I/PTG

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6520/8520/6620/8620/6720/8720
SLEEP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
† If WDT causes wake-up, this bit is cleared.
DS39609B-page 294
Q Cycle Activity:
Before Instruction
After Instruction
Decode
TO =
PD =
TO =
PD =
Q1
?
?
1 †
0
operation
Enter SLEEP mode
[ label ] SLEEP
None
00h
0
1
0
TO, PD
The Power-down status bit (PD) is
cleared. The Time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
1
1
SLEEP
Q2
No
0000
WDT postscaler,
TO,
PD
WDT,
0000
Process
Data
Q3
0000
Sleep
Go to
Q4
0011
SUBFWB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ‘f’
(W) – (f) – (C)
N, OV, C, DC, Z
Subtract f from W with borrow
[ label ] SUBFWB
0
d
a
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored in register ‘f’ (default). If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
1
1
SUBFWB
SUBFWB
SUBFWB
Read
Q2
0101
3
2
1
FF
2
0
0
1
2
5
1
2
3
1
0
0
1
2
0
0
2
1
1
0
 2004 Microchip Technology Inc.
f
[0,1]
[0,1]
; result is negative
; result is positive
; result is zero
255
01da
REG, 1, 0
REG, 0, 0
REG, 1, 0
Process
Data
Q3
dest
ffff
f [,d [,a]
destination
Write to
Q4
ffff