PIC18LF8520-I/PTG Microchip Technology, PIC18LF8520-I/PTG Datasheet - Page 153

• Manufacturer Part Number: PIC18LF8520-I/PTG
• Description: IC MCU FLASH 16KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8520-I/PTG

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.2
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on pin RC2/CCP1. An event is defined as one of
the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set; it must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
16.2.1
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.
16.2.2
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode,
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work. The
timer to be used with each CCP module is selected in the
T3CON register (see Section 16.1.1 “CCP Modules
and Timer Resources”).
FIGURE 16-2:
 2004 Microchip Technology Inc.
Note:
Capture Mode
CCP1 pin
CCP PIN CONFIGURATION
If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
TIMER1/TIMER3 MODE SELECTION
PIC18F6520/8520/6620/8620/6720/8720
CAPTURE MODE OPERATION BLOCK DIAGRAM
Q’s
Edge Detect
Prescaler
1, 4, 16
and
CCP1CON<3:0>
Set Flag bit CCP1IF
T3CCP2
T3CCP2
16.2.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
16.2.4
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 16-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 16-1:
CLRF
MOVLW
MOVWF
CCP1CON, F
NEW_CAPT_PS ; Load WREG with the
CCP1CON
SOFTWARE INTERRUPT
CCP PRESCALER
TMR1
Enable
TMR3
Enable
CCPR1H
TMR1H
TMR3H
CHANGING BETWEEN
CAPTURE PRESCALERS
; Turn CCP module off
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
CCPR1L
TMR3L
TMR1L
DS39609B-page 151