ATMEGA162V-1MC Atmel, ATMEGA162V-1MC Datasheet - Page 163
![IC MCU AVR 16K 1.8V 8MHZ 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA162V-1MC
Manufacturer Part Number
ATMEGA162V-1MC
Description
IC MCU AVR 16K 1.8V 8MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA162V-1MC
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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USART
Dual USART
2513C–AVR–09/02
The Universal Synchronous and Asynchronous serial Receiver and Transmitter
(USART) is a highly flexible serial communication device. The main features are:
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The ATmega162 has two USARTs, USART0 and USART1. The functionality for both
USARTs is described below.
USART0 and USART1 have different I/O Registers as shown in “Register Summary” on
page 272. Note that in ATmega161 compatibility mode, the double buffering of the
USART Receive Register is disabled. For details, see “AVR USART vs. AVR UART –
Compatibility” on page 165. Note also that the shared UBRRHI Register in ATmega161
has been split into two seperate registers, UBRR0H and UBRR1H, in ATmega162.
A simplified block diagram of the USART Transmitter is shown in Figure 75. CPU acces-
sible I/O Registers and I/O pins are shown in bold.
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
ATmega162(V/U/L)
163
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