ATMEGA162V-1MC Atmel, ATMEGA162V-1MC Datasheet - Page 139
![IC MCU AVR 16K 1.8V 8MHZ 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA162V-1MC
Manufacturer Part Number
ATMEGA162V-1MC
Description
IC MCU AVR 16K 1.8V 8MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA162V-1MC
Core Processor
AVR
Core Size
8-Bit
Speed
1MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
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Force Output Compare
Compare Match Blocking by
TCNT2 Write
Using the Output Compare
Unit
2513C–AVR–09/02
Figure 61. Output Compare Unit, Block Diagram
The OCR2 Register is double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR2 Compare Register to either top or bottom of the counting sequence. The synchro-
nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR2 Register access may seem complex, but this is not case. When the double
buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double
buffering is disabled the CPU will access the OCR2 directly.
In non-PWM waveform generation modes, the match output of the comparator can be
forced by writing a one to the Force Output Compare (FOC2) bit. Forcing compare
match will not set the OCF2 flag or reload/clear the timer, but the OC2 pin will be
updated as if a real compare match had occurred (the COM21:0 bits settings define
whether the OC2 pin is set, cleared or toggled).
All CPU write operations to the TCNT2 Register will block any compare match that
occurs in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when
the Timer/Counter clock is enabled.
Since writing TCNT2 in any mode of operation will block all compare matches for one
timer clock cycle, there are risks involved when changing TCNT2 when using the output
compare channel, independently of whether the Timer/Counter is running or not. If the
value written to TCNT2 equals the OCR2 value, the compare match will be missed,
bottom
FOCn
OCRn
top
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
COMn1:0
ATmega162(V/U/L)
TCNTn
OCFn (Int.Req.)
OCxy
139
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