ATMEGA161L-4PC Atmel, ATMEGA161L-4PC Datasheet - Page 71
ATMEGA161L-4PC
Manufacturer Part Number
ATMEGA161L-4PC
Description
IC AVR MCU 16K LV 4MHZ COM 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA161-8AC.pdf
(159 pages)
Specifications of ATMEGA161L-4PC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
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Data Reception
1228D–AVR–02/07
Figure 45 shows a block diagram of the UART Receiver.
Figure 45. UART Receiver
The Receiver front-end logic samples the signal on the RXDn pin at a frequency 16
times the baud rate. While the line is idle, one single sample of logical “0” will be inter-
preted as the falling edge of a start bit, and the start bit detection sequence is initiated.
Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the Receiver
samples the RXDn pin at samples 8, 9 and 10. If two or more of these three samples are
found to be logical “1”s, the start bit is rejected as a noise spike and the Receiver starts
looking for the next 1-to-0 transition.
If, however, a valid start bit is detected, sampling of the data bits following the start bit is
performed. These bits are also sampled at samples 8, 9 and 10. The logical value found
in at least two of the three samples is taken as the bit value. All bits are shifted into the
Transmitter Shift Register as they are sampled. Sampling of an incoming character is
shown in Figure 46. Note that the description above is not valid when the UART trans-
mission speed is doubled. See “Double-speed Transmission” on page 78 for a detailed
description.
XTAL
PD0/
PB2
PIN CONTROL
GENERATOR
n = 0,1
BAUD RATE
LOGIC
RXDn
BAUD x 16
DATA RECOVERY
LOGIC
UART CONTROL AND
STATUS REGISTER
DATA BUS
/16
(UCSRnB)
STORE UDRn
BAUD
DATA BUS
RXCn
IRQ
UART CONTROL AND
STATUS REGISTER
ATmega161(L)
SHIFT REGISTER
REGISTER (UDRn)
(UCSRnA)
10(11)-BIT RX
UART I/O DATA
71
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