ATMEGA323-8PC Atmel, ATMEGA323-8PC Datasheet - Page 49
![IC AVR MCU 32K 8MHZ COM 40DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA323-8PC
Manufacturer Part Number
ATMEGA323-8PC
Description
IC AVR MCU 32K 8MHZ COM 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA323L-4PC.pdf
(247 pages)
Specifications of ATMEGA323-8PC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
ATMEGA3238PC
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Timer Counter0 – TCNT0
Timer/Counter2 – TCNT2
Timer/Counter0 Output
Compare Register – OCR0
Timer/Counter2 Output
Compare Register – OCR2
Timer/Counter 0 and 2 in PWM
Mode
1457G–AVR–09/03
The Stop condition provides a Timer Enable/Disable function. The prescaled modes are
scaled directly from the CK Oscillator clock for Timer/Counter0 and PCK2 for
Timer/Counter2. If the external pin modes are used for Timer/Counter0, transitions on
PB0(T0) will clock the counter even if the pin is configured as an output. This feature
can give the user SW control of the counting.
These 8-bit registers contain the value of the Timer/Counters.
Both Timer/Counters is realized as up or up/down (in PWM mode) counters with read
and write access. If the Timer/Counter is written to and a clock source is selected, it con-
tinues counting in the timer clock cycle following the write operation.
The Output Compare Registers are 8-bit read/write registers. The Timer/Counter Output
Compare Registers contains the data to be continuously compared with the
Timer/Counter. Actions on compare matches are specified in TCCR0 and TCCR2. A
software write to the Timer/Counter Register blocks compare matches in the next
Timer/Counter clock cycle. This prevents immediate interrupts when initializing the
Timer/Counter.
A Compare Match will set the Compare Interrupt Flag in the CPU clock cycle following
the compare event.
When PWM mode is selected, the Timer/Counter either wraps (overflows) when it
reaches $FF or it acts as an up/down counter.
If the up/down mode is selected, the Timer/Counter and the Output Compare Registers
– OCR0 or OCR2 form an 8-bit, free running, glitch-free and phase correct PWM with
outputs on the PB3(OC0/PWM0) or PD7(OC2/PWM2) pin.
If the overflow mode is selected, the Timer/Counter and the Output Compare Registers
– OCR0 or OCR2 form an 8-bit, free running and glitch-free PWM, operating with twice
the speed of the up/down counting mode.
Bit
$32 ($52)
Read/Write
Initial Value
Bit
$24 ($44)
Read/Write
Initial Value
Bit
$3C ($5C)
Read/Write
Initial Value
Bit
$23 ($43)
Read/Write
Initial Value
MSB
MSB
MSB
MSB
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
ATmega323(L)
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
LSB
R/W
LSB
R/W
LSB
R/W
LSB
R/W
0
0
0
0
0
0
0
0
TCNT0
TCNT2
OCR0
OCR2
49
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