ATMEGA323-8PC Atmel, ATMEGA323-8PC Datasheet - Page 34

• Manufacturer Part Number: ATMEGA323-8PC
• Description: IC AVR MCU 32K 8MHZ COM 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA323-8PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA3238PC

The General Interrupt Flag
Register – GIFR
The Timer/Counter Interrupt
Mask Register – TIMSK
34
ATmega323(L)
Note: If Boot Lock bits BLB02 or BLB12 are set, changing the Interrupt Vector table will
change from what part of the Program memory interrupts are allowed. Refer to the sec-
tion “Boot Loader Support” on page 177 for details on Boot Lock bits.
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be set to enable change of the IVSEL bit. IVCE is cleared by hard-
ware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will
disable interrupts, as explained in the IVSEL description above.
• Bit 7 – INTF1: External Interrupt Flag1
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one).
If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT1 is configured as a level interrupt.
• Bit 6 – INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT0 is configured as a level interrupt.
• Bit 5 – INTF2: External Interrupt Flag2
When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one).
If the I-bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATmega323 and always read as zero.
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is
executed if a compare match in Timer/Counter2 occurs, i.e. when the OCF2 bit is set in
the Timer/Counter Interrupt Flag Register
Bit
$3A ($5A)
Read/Write
Initial Value
Bit
$39 ($59)
Read/Write
Initial Value
OCIE2
INTF1
R/W
R/W
7
0
7
0
INTF0
TOIE2
R/W
R/W
6
0
6
0
TICIE1
INTF2
R/W
R/W
5
0
5
0
OCIE1A
R/W
R
4
–
0
4
0
–
TIFR.
OCIE1B
R/W
R
3
–
0
3
0
TOIE1
R/W
R
2
–
0
2
0
OCIE0
R/W
R
1
–
0
1
0
TOIE0
R/W
1457G–AVR–09/03
R
0
–
0
0
0
TIMSK
GIFR